[llvm] r360228 - [CodeGenPrepare] Don't split the store if it is volatile

[QingShan Zhang via llvm-commits]

Author: qshanz
Date: Wed May  8 00:32:12 2019
New Revision: 360228

URL: http://llvm.org/viewvc/llvm-project?rev=360228&view=rev
Log:
[CodeGenPrepare] Don't split the store if it is volatile
We shouldn't split the store when it is volatile.

Differential Revision: https://reviews.llvm.org/D61169

Added:
    llvm/trunk/test/CodeGen/PowerPC/splitstore-check-volatile.ll
Modified:
    llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp?rev=360228&r1=360227&r2=360228&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp Wed May  8 00:32:12 2019
@@ -6657,6 +6657,10 @@ static bool splitMergedValStore(StoreIns
       DL.getTypeSizeInBits(SplitStoreType))
     return false;
 
+  // Don't split the store if it is volatile.
+  if (SI.isVolatile())
+    return false;
+
   // Match the following patterns:
   // (store (or (zext LValue to i64),
   //            (shl (zext HValue to i64), 32)), HalfValBitSize)

Added: llvm/trunk/test/CodeGen/PowerPC/splitstore-check-volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/splitstore-check-volatile.ll?rev=360228&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/splitstore-check-volatile.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/splitstore-check-volatile.ll Wed May  8 00:32:12 2019
@@ -0,0 +1,17 @@
+; Test that CodeGenPrepare respect the volatile flag when splitting a store.
+;
+; RUN: opt -S -codegenprepare -force-split-store < %s  | FileCheck %s
+
+define void @fun(i16* %Src, i16* %Dst) {
+; CHECK: store volatile i16 %8, i16* %Dst 
+  %1 = load i16, i16* %Src
+  %2 = trunc i16 %1 to i8
+  %3 = lshr i16 %1, 8
+  %4 = trunc i16 %3 to i8
+  %5 = zext i8 %2 to i16
+  %6 = zext i8 %4 to i16
+  %7 = shl nuw i16 %6, 8
+  %8 = or i16 %7, %5
+  store volatile i16 %8, i16* %Dst
+  ret void
+}