[PATCH] D61658: [PowerPC] Emit XXSEL for vec_sel and code that has the same pattern

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, jsji, stefanp.
Herald added a subscriber: kbarton.
Herald added a project: LLVM.

As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777
we do not emit a vector select even when the pretty much asks for one. This patch changes that.


Repository:
  rL LLVM

https://reviews.llvm.org/D61658

Files:
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/vec-select.ll


Index: test/CodeGen/PowerPC/vec-select.ll
===================================================================
--- test/CodeGen/PowerPC/vec-select.ll
+++ test/CodeGen/PowerPC/vec-select.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr7 -ppc-asm-full-reg-names < %s | FileCheck %s
+define dso_local <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
+; CHECK-NEXT:    blr
+entry:
+  %neg.i = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and.i = and <4 x i32> %neg.i, %a
+  %and1.i = and <4 x i32> %c, %b
+  %or.i = or <4 x i32> %and.i, %and1.i
+  ret <4 x i32> %or.i
+}
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -958,6 +958,13 @@
 
 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
+def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
+                     (and v4i32:$B, v4i32:$C))),
+          (v4i32 (XXSEL $A, $B, $C))>;
+def : Pat<(v4i32 (or (and v4i32:$A, (vnot_ppc v4i32:$C)),
+                     (and v4i32:$B, v4i32:$C))),
+          (v4i32 (XXSEL $A, $B, $C))>;
+
 let Predicates = [IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;


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