[PATCH] D61546: Stop the DAG combiner from combining vector stores greater than preferred vector width...

[Eric Christopher via Phabricator via llvm-commits]

echristo closed this revision.
echristo added a comment.

This happened here:

echristo at athyra ~/r/llvm-project> git llvm push
Pushing 1 commit:

  96aa9dda693 Make sure that the DAG combiner doesn't merge stores that we explicitly asked not be greater than preferred vector width for the vectorizer. Test for both 128 and 256 with a skylake architecture.

Sending        llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Adding         llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll
Transmitting file data ..done
Committing transaction...
Committed revision 360183.
Committed 96aa9dda693 to svn.

I'm bad at remembering to add it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61546/new/

https://reviews.llvm.org/D61546