[PATCH] D61490: AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL360123: AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand (authored by nha, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D61490?vs=197958&id=198417#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61490/new/

https://reviews.llvm.org/D61490

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir


Index: llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir
@@ -0,0 +1,21 @@
+# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: S_CMP_EQ_U32
+
+# CHECK-NOT: Bad machine code
+
+---
+name: sop2_sopc
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0:sreg_32_xm0 = S_ADD_I32 2011, -113, implicit-def $scc
+    S_CMP_EQ_U32 2011, -113, implicit-def $scc
+
+    %1:sreg_32_xm0 = S_SUB_I32 2011, 10, implicit-def $scc
+    S_CMP_LG_U32 -5, 2011, implicit-def $scc
+...
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3191,6 +3191,24 @@
     }
   }
 
+  if (isSOP2(MI) || isSOPC(MI)) {
+    const MachineOperand &Src0 = MI.getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI.getOperand(Src1Idx);
+    unsigned Immediates = 0;
+
+    if (!Src0.isReg() &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
+      Immediates++;
+    if (!Src1.isReg() &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
+      Immediates++;
+
+    if (Immediates > 1) {
+      ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
+      return false;
+    }
+  }
+
   if (isSOPK(MI)) {
     auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
     if (Desc.isBranch()) {


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