[PATCH] D61582: [SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, rnk.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

It's possible to use the 'y' mmx constraint with a type narrower than 64-bits.

This patch supports this by bitcasting the mmx type to 64-bits and then
truncating to the desired type.

There are probably other missing type combinations we need to support, but this
is the case we have a bug report for.

Fixes PR41748.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D61582

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/X86/pr41748.ll


Index: llvm/test/CodeGen/X86/pr41748.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr41748.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.14.0 -mattr=mmx | FileCheck %s
+
+define i32 @foo(i32 %a) {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    movd %edi, %mm0
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i32 asm sideeffect "movd    $1, $0", "=y,r,~{dirflag},~{fpsr},~{flags}"(i32 %a)
+  ret i32 %0
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -322,6 +322,15 @@
     return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
   }
 
+  // Handle MMX to a narrower integer type by bitcasting MMX to integer and
+  // then truncating.
+  if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
+      ValueVT.bitsLT(PartEVT)) {
+    PartEVT = EVT::getIntegerVT(*DAG.getContext(),  PartEVT.getSizeInBits());
+    Val = DAG.getNode(ISD::BITCAST, DL, PartEVT, Val);
+    return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
+  }
+
   report_fatal_error("Unknown mismatch in getCopyFromParts!");
 }
 


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