[PATCH] D52109: [TwoAddressInstructionPass] Don't update SrcRegMap for copies inserted for tied register constraint when the src isn't killed

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 198062.
craig.topper added a comment.
Herald added a subscriber: hiraditya.

Rebase


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52109/new/

https://reviews.llvm.org/D52109

Files:
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/avx512bw-mask-op.ll
  llvm/test/CodeGen/X86/avx512dq-mask-op.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/bswap_tree2.ll
  llvm/test/CodeGen/X86/bypass-slow-division-32.ll
  llvm/test/CodeGen/X86/combine-fcopysign.ll
  llvm/test/CodeGen/X86/combine-mul.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/combine-sra.ll
  llvm/test/CodeGen/X86/combine-srem.ll
  llvm/test/CodeGen/X86/combine-srl.ll
  llvm/test/CodeGen/X86/combine-udiv.ll
  llvm/test/CodeGen/X86/dagcombine-shifts.ll
  llvm/test/CodeGen/X86/fshl.ll
  llvm/test/CodeGen/X86/fshr.ll
  llvm/test/CodeGen/X86/funnel-shift.ll
  llvm/test/CodeGen/X86/haddsub-undef.ll
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/imul.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
  llvm/test/CodeGen/X86/mul-constant-i16.ll
  llvm/test/CodeGen/X86/mul-constant-i32.ll
  llvm/test/CodeGen/X86/mul-constant-i64.ll
  llvm/test/CodeGen/X86/mul-constant-i8.ll
  llvm/test/CodeGen/X86/palignr.ll
  llvm/test/CodeGen/X86/phaddsub.ll
  llvm/test/CodeGen/X86/pmul.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/powi.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/rotate-extract.ll
  llvm/test/CodeGen/X86/rotate-multi.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/sqrt-fastmath.ll
  llvm/test/CodeGen/X86/sse-minmax.ll
  llvm/test/CodeGen/X86/sse2-intrinsics-canonical.ll
  llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/uadd_sat_vec.ll
  llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
  llvm/test/CodeGen/X86/usub_sat_vec.ll
  llvm/test/CodeGen/X86/vec_ctbits.ll
  llvm/test/CodeGen/X86/vec_minmax_sint.ll
  llvm/test/CodeGen/X86/vec_minmax_uint.ll
  llvm/test/CodeGen/X86/vec_saddo.ll
  llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
  llvm/test/CodeGen/X86/vec_shift6.ll
  llvm/test/CodeGen/X86/vec_smulo.ll
  llvm/test/CodeGen/X86/vec_ssubo.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-ext-logic.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
  llvm/test/CodeGen/X86/vector-lzcnt-128.ll
  llvm/test/CodeGen/X86/vector-mul.ll
  llvm/test/CodeGen/X86/vector-popcnt-128.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul.ll
  llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128-widen.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector-tzcnt-128.ll
  llvm/test/CodeGen/X86/vselect-minmax.ll
  llvm/test/CodeGen/X86/vselect-zero.ll
  llvm/test/CodeGen/X86/x86-shifts.ll

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