[PATCH] D61516: [SelectionDAG] fold 'fneg undef' to undef

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 3 09:53:20 PDT 2019


arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/X86/vec_fneg.ll:52
-; X64-SSE2-NEXT:    retq
+; X64-SSE-LABEL: scalar_fsub_neg0_undef:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    retq
   %r = fsub float -0.0, undef
   ret float %r
----------------
spatel wrote:
> arsenm wrote:
> > It seems problematic that the DAG lowering is still producing an fneg for this
> I'm not following. Is there some place before/after getNode() that we should also fix?
I mean I don't expect fsub -0, x to be equivalent to fneg x anymore. This test shouldn't be hitting this path, and should be using the fneg instruction?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61516/new/

https://reviews.llvm.org/D61516





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