[PATCH] D61499: Make sub-registers index names case sensitive in the MIRParser

[Markus Lavin via Phabricator via llvm-commits]

markus created this revision.
markus added reviewers: arsenm, arphaman.
Herald added subscribers: dexonsmith, wdng.
Herald added a project: LLVM.

Prior to this change sub-register index names are assumed to be lower case (but they are printed with original casing). This means that if a target has some upper case characters in its sub-register names then mir-export directly followed by mir-import is not possible. This also means that sub-register indices currently are (and will continue to be) slightly inconsistent with register names which are printed and assumed to be lower case.

As the current textual representation of mir has a few inconsistencies in this area it is a bit arbitrary how to address this but the suggested change is towards the direction that we feel is most correct (i.e. case sensitivity).


Repository:
  rL LLVM

https://reviews.llvm.org/D61499

Files:
  lib/CodeGen/MIRParser/MIParser.cpp


Index: lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIParser.cpp
+++ lib/CodeGen/MIRParser/MIParser.cpp
@@ -176,7 +176,7 @@
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   for (unsigned I = 1, E = TRI->getNumSubRegIndices(); I < E; ++I)
     Names2SubRegIndices.insert(
-        std::make_pair(StringRef(TRI->getSubRegIndexName(I)).lower(), I));
+        std::make_pair(TRI->getSubRegIndexName(I), I));
 }
 
 unsigned PerTargetMIParsingState::getSubRegIndex(StringRef Name) {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D61499.197974.patch
Type: text/x-patch
Size: 579 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190503/6d0be83c/attachment-0001.bin>