[PATCH] D61429: AMDGPU: Remove redundant patterns for sub

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

There were 2 patterns for sub, one selecting to sub and one to
subrev. Only one of these will succeed, so remove the reversed one.


https://reviews.llvm.org/D61429

Files:
  lib/Target/AMDGPU/VOP2Instructions.td


Index: lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP2Instructions.td
+++ lib/Target/AMDGPU/VOP2Instructions.td
@@ -528,16 +528,12 @@
 let SubtargetPredicate = HasAddNoCarryInsts in {
   def : DivergentBinOp<add, V_ADD_U32_e32>;
   def : DivergentBinOp<sub, V_SUB_U32_e32>;
-  def : DivergentBinOp<sub, V_SUBREV_U32_e32>;
 }
 
 let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
 def : DivergentBinOp<add, V_ADD_I32_e32>;
-
 def : DivergentBinOp<sub, V_SUB_I32_e32>;
 
-def : DivergentBinOp<sub, V_SUBREV_I32_e32>;
-
 def : DivergentBinOp<srl, V_LSHRREV_B32_e32>;
 def : DivergentBinOp<sra, V_ASHRREV_I32_e32>;
 def : DivergentBinOp<shl, V_LSHLREV_B32_e32>;


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