[PATCH] D60706: [ARM] implement 8.1-M instructions at the MC level.

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:200
 def FPINST2 : ARMReg<10, "fpinst2">;
+// These encodings aren't actual instruction encodings, their encoding depends
+// on the instruction they are used in and for VPR 32 was chosen such that it
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Hi Simon, I started  looking into this too. I will leave some drive-by comments of a few things I spotted.
Don't think I understand  the comments here, i.e. I don't see why we talk about instruction encondings while we are describing registers here.


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Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:207
+def P0      : ARMReg<13, "p0">;
+def FPCXTNS : ARMReg<14, "fpcxtns">;
+def FPCXTS  : ARMReg<15, "fpcxts">;
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Reading the ARM ARM, I don't think we need this register description. In fact, it's unused in the code at the moment, so if it turns out we need something like this it can be added later.




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  https://reviews.llvm.org/D60706/new/

https://reviews.llvm.org/D60706