[PATCH] D61400: [SelectionDAG] Utilize ARM shift behavior

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Wouldn't it be better/safer to create ARMISD shift opcodes to handle this behaviour?

Agreed; we make assumptions about ISD::SHL etc. all over; changing that would be a lot of work, and might end up pessimizing code overall.

> I was under the impression that the shift was by the bottom byte amount. i.e the mask is 255, and a shift of 256 is the same as a shift of 0. I have not tried it though.

This is true for NEON vectors, not scalars, as far as I can tell.

> For aarch64 the mask may to be the size of the datatype. The armarm will contain the correct information if you can decipher the pseudo code.

Yes, lslv etc. masks the shift amount by the operand size.


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