[PATCH] D61400: [SelectionDAG] Utilize ARM shift behavior

[Shawn Landden via Phabricator via llvm-commits]

shawnl created this revision.
shawnl added reviewers: bjope, spatel, RKSimon, nikic.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar.
Herald added a project: LLVM.

LLVM-IR shifts have UB if the shift amount is equal to or greater to
the shift range, but a number of architectures have well-defined
behavior in this case.

     

Utilize the behavior of ARM for shl and lshr to remove some code,
as can be seen in the tests.

Fixes PR41363


Repository:
  rL LLVM

https://reviews.llvm.org/D61400

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/AArch64/unguard-shifts.ll
  test/CodeGen/ARM/unguard-shifts.ll

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