[llvm] r359457 - [AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 29 08:27:28 PDT 2019
Author: c-rhodes
Date: Mon Apr 29 08:27:27 2019
New Revision: 359457
URL: http://llvm.org/viewvc/llvm-project?rev=359457&view=rev
Log:
[AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions
This patch adds aliases for element sizes .B/.H/.S to the
AND/ORR/EOR/BIC bitwise logical instructions. The assembler now accepts
these instructions with all element sizes up to 64-bit (.D). The
preferred disassembly is .D.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/and.s
llvm/trunk/test/MC/AArch64/SVE/bic.s
llvm/trunk/test/MC/AArch64/SVE/eor.s
llvm/trunk/test/MC/AArch64/SVE/orr.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Apr 29 08:27:27 2019
@@ -25,10 +25,10 @@ let Predicates = [HasSVE] in {
defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
- def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
- def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
- def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
- def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
+ defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
+ defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
+ defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
+ defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Apr 29 08:27:27 2019
@@ -1982,6 +1982,16 @@ class sve_int_bin_cons_log<bits<2> opc,
let Inst{4-0} = Zd;
}
+multiclass sve_int_bin_cons_log<bits<2> opc, string asm> {
+ def NAME : sve_int_bin_cons_log<opc, asm>;
+
+ def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+ (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
+ def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+ (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
+ def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+ (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
+}
//===----------------------------------------------------------------------===//
// SVE Integer Wide Immediate - Predicated Group
Modified: llvm/trunk/test/MC/AArch64/SVE/and.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/and.s?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/and.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/and.s Mon Apr 29 08:27:27 2019
@@ -111,6 +111,28 @@ and p15.b, p15/z, p15.b, p15.b
// --------------------------------------------------------------------------//
+// Test aliases.
+
+and z0.s, z0.s, z0.s
+// CHECK-INST: and z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and z0.h, z0.h, z0.h
+// CHECK-INST: and z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and z0.b, z0.b, z0.b
+// CHECK-INST: and z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
Modified: llvm/trunk/test/MC/AArch64/SVE/bic.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/bic.s?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/bic.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/bic.s Mon Apr 29 08:27:27 2019
@@ -105,6 +105,28 @@ bic p0.b, p0/z, p0.b, p0.b
// --------------------------------------------------------------------------//
+// Test aliases.
+
+bic z0.s, z0.s, z0.s
+// CHECK-INST: bic z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic z0.h, z0.h, z0.h
+// CHECK-INST: bic z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic z0.b, z0.b, z0.b
+// CHECK-INST: bic z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
Modified: llvm/trunk/test/MC/AArch64/SVE/eor.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eor.s?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eor.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/eor.s Mon Apr 29 08:27:27 2019
@@ -111,6 +111,28 @@ eor p15.b, p15/z, p15.b, p15.b
// --------------------------------------------------------------------------//
+// Test aliases.
+
+eor z0.s, z0.s, z0.s
+// CHECK-INST: eor z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor z0.h, z0.h, z0.h
+// CHECK-INST: eor z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor z0.b, z0.b, z0.b
+// CHECK-INST: eor z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.b, p7/z, z6.b
Modified: llvm/trunk/test/MC/AArch64/SVE/orr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orr.s?rev=359457&r1=359456&r2=359457&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orr.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orr.s Mon Apr 29 08:27:27 2019
@@ -113,6 +113,46 @@ orr p15.b, p15/z, p15.b, p15.b
// --------------------------------------------------------------------------//
+// Test aliases.
+
+orr z0.s, z0.s, z0.s
+// CHECK-INST: mov z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr z0.h, z0.h, z0.h
+// CHECK-INST: mov z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr z0.b, z0.b, z0.b
+// CHECK-INST: mov z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr z23.s, z13.s, z8.s // should not use mov-alias
+// CHECK-INST: orr z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr z23.h, z13.h, z8.h // should not use mov-alias
+// CHECK-INST: orr z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr z23.b, z13.b, z8.b // should not use mov-alias
+// CHECK-INST: orr z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
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