[PATCH] D61045: [AMDGPU] gfx1010 sgpr register changes
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 10:38:57 PDT 2019
arsenm added inline comments.
================
Comment at: llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc.cpp:327
"s[84:85]", "s[86:87]", "s[88:89]", "s[90:91]", "s[92:93]", "s[94:95]",
- "s[96:97]", "s[98:99]", "s[100:101]", "s[102:103]"
+ "s[96:97]", "s[98:99]", "s[100:101]", "s[102:103]", "s[104:105]"
};
----------------
Needs tests for the new regs
================
Comment at: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:4278
+ case ID_GS_ALLOC_REQ:
+ if (isSI() || isCI() || isVI())
+ continue;
----------------
Should be a hasX function
================
Comment at: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:1044-1045
+ if (Id == ID_INTERRUPT ||
+ (Id == ID_GS_ALLOC_REQ && !AMDGPU::isSI(STI) && !AMDGPU::isCI(STI) &&
+ !AMDGPU::isVI(STI))) {
if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0.
----------------
This should be at least wrapped in a hasX function
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D61045/new/
https://reviews.llvm.org/D61045
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