[llvm] r359231 - [GlobalISel][AArch64] Make G_EXTRACT_VECTOR_ELT legal for v8s16s

[Jessica Paquette via llvm-commits]

Author: paquette
Date: Thu Apr 25 13:00:57 2019
New Revision: 359231

URL: http://llvm.org/viewvc/llvm-project?rev=359231&view=rev
Log:
[GlobalISel][AArch64] Make G_EXTRACT_VECTOR_ELT legal for v8s16s

This case was missing before, so we couldn't legalize it.

Add it to AArch64LegalizerInfo.cpp and update select-extract-vector-elt.mir.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=359231&r1=359230&r2=359231&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Apr 25 13:00:57 2019
@@ -517,8 +517,8 @@ AArch64LegalizerInfo::AArch64LegalizerIn
       .minScalar(2, s64)
       .legalIf([=](const LegalityQuery &Query) {
         const LLT &VecTy = Query.Types[1];
-        return VecTy == v2s16 || VecTy == v4s16 || VecTy == v4s32 ||
-               VecTy == v2s64 || VecTy == v2s32;
+        return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 ||
+               VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32;
       });
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir?rev=359231&r1=359230&r2=359231&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir Thu Apr 25 13:00:57 2019
@@ -115,3 +115,26 @@ body:             |
     RET_ReallyLR implicit $h0
 
 ...
+---
+name:            v8s16_fpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v8s16_fpr
+    ; CHECK: liveins: $q0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
+    ; CHECK: $h0 = COPY [[CPYi16_]]
+    ; CHECK: RET_ReallyLR implicit $h0
+    %0:fpr(<8 x s16>) = COPY $q0
+    %2:gpr(s64) = G_CONSTANT i64 1
+    %3:fpr(s64) = COPY %2(s64)
+    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
+    $h0 = COPY %1(s16)
+    RET_ReallyLR implicit $h0
+
+...