[llvm] r359204 - [GlobalISel][AArch64] Legalize G_FNEARBYINT
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 25 09:44:40 PDT 2019
Author: paquette
Date: Thu Apr 25 09:44:40 2019
New Revision: 359204
URL: http://llvm.org/viewvc/llvm-project?rev=359204&view=rev
Log:
[GlobalISel][AArch64] Legalize G_FNEARBYINT
Add legalizer support for G_FNEARBYINT. It's the same as G_FCEIL etc.
Since the importer allows us to automatically select this after legalization,
also add tests for selection etc. Also update arm64-vfloatintrinsics.ll.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=359204&r1=359203&r2=359204&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Apr 25 09:44:40 2019
@@ -1323,6 +1323,7 @@ LegalizerHelper::widenScalar(MachineInst
case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FRINT:
+ case TargetOpcode::G_FNEARBYINT:
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FEXP:
case TargetOpcode::G_FEXP2:
@@ -2191,6 +2192,7 @@ LegalizerHelper::fewerElementsVector(Mac
case G_FLOG:
case G_FLOG2:
case G_FLOG10:
+ case G_FNEARBYINT:
case G_FCEIL:
case G_FFLOOR:
case G_FRINT:
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=359204&r1=359203&r2=359204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Apr 25 09:44:40 2019
@@ -131,7 +131,8 @@ AArch64LegalizerInfo::AArch64LegalizerIn
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
- G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
+ G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
+ G_FNEARBYINT})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
.fewerElementsIf(
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=359204&r1=359203&r2=359204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Apr 25 09:44:40 2019
@@ -396,6 +396,7 @@ static bool isPreISelGenericFloatingPoin
case TargetOpcode::G_FPTRUNC:
case TargetOpcode::G_FCEIL:
case TargetOpcode::G_FFLOOR:
+ case TargetOpcode::G_FNEARBYINT:
case TargetOpcode::G_FNEG:
case TargetOpcode::G_FCOS:
case TargetOpcode::G_FSIN:
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir?rev=359204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir Thu Apr 25 09:44:40 2019
@@ -0,0 +1,234 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
+
+...
+---
+name: test_v4f16.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; FP16-LABEL: name: test_v4f16.nearbyint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(<4 x s16>) = G_FNEARBYINT [[COPY]]
+ ; FP16: $d0 = COPY [[FNEARBYINT]](<4 x s16>)
+ ; FP16: RET_ReallyLR implicit $d0
+ ; NO-FP16-LABEL: name: test_v4f16.nearbyint
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NO-FP16: [[FNEARBYINT1:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT1]]
+ ; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT1]](s32)
+ ; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NO-FP16: [[FNEARBYINT2:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT2]]
+ ; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT2]](s32)
+ ; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NO-FP16: [[FNEARBYINT3:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT3]]
+ ; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT3]](s32)
+ ; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
+ ; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; FP16-LABEL: name: test_v8f16.nearbyint
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(<8 x s16>) = G_FNEARBYINT [[COPY]]
+ ; FP16: $q0 = COPY [[FNEARBYINT]](<8 x s16>)
+ ; FP16: RET_ReallyLR implicit $q0
+ ; NO-FP16-LABEL: name: test_v8f16.nearbyint
+ ; NO-FP16: liveins: $q0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NO-FP16: [[FNEARBYINT1:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT1]]
+ ; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT1]](s32)
+ ; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NO-FP16: [[FNEARBYINT2:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT2]]
+ ; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT2]](s32)
+ ; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NO-FP16: [[FNEARBYINT3:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT3]]
+ ; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT3]](s32)
+ ; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
+ ; NO-FP16: [[FNEARBYINT4:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT4]]
+ ; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT4]](s32)
+ ; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
+ ; NO-FP16: [[FNEARBYINT5:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT5]]
+ ; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT5]](s32)
+ ; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
+ ; NO-FP16: [[FNEARBYINT6:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT6]]
+ ; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT6]](s32)
+ ; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
+ ; NO-FP16: [[FNEARBYINT7:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT7]]
+ ; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT7]](s32)
+ ; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
+ ; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; FP16-LABEL: name: test_v2f32.nearbyint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s32>) = G_FNEARBYINT [[COPY]]
+ ; FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
+ ; FP16: RET_ReallyLR implicit $d0
+ ; NO-FP16-LABEL: name: test_v2f32.nearbyint
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s32>) = G_FNEARBYINT [[COPY]]
+ ; NO-FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v2f64.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; FP16-LABEL: name: test_v2f64.nearbyint
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s64>) = G_FNEARBYINT [[COPY]]
+ ; FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
+ ; FP16: RET_ReallyLR implicit $q0
+ ; NO-FP16-LABEL: name: test_v2f64.nearbyint
+ ; NO-FP16: liveins: $q0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s64>) = G_FNEARBYINT [[COPY]]
+ ; NO-FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(<2 x s64>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_f32.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; FP16-LABEL: name: test_f32.nearbyint
+ ; FP16: liveins: $s0
+ ; FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[COPY]]
+ ; FP16: $s0 = COPY [[FNEARBYINT]](s32)
+ ; FP16: RET_ReallyLR implicit $s0
+ ; NO-FP16-LABEL: name: test_f32.nearbyint
+ ; NO-FP16: liveins: $s0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[COPY]]
+ ; NO-FP16: $s0 = COPY [[FNEARBYINT]](s32)
+ ; NO-FP16: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %1:_(s32) = G_FNEARBYINT %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; FP16-LABEL: name: test_f64.nearbyint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(s64) = G_FNEARBYINT [[COPY]]
+ ; FP16: $d0 = COPY [[FNEARBYINT]](s64)
+ ; FP16: RET_ReallyLR implicit $d0
+ ; NO-FP16-LABEL: name: test_f64.nearbyint
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s64) = G_FNEARBYINT [[COPY]]
+ ; NO-FP16: $d0 = COPY [[FNEARBYINT]](s64)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_FNEARBYINT %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_f16.nearbyint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; FP16-LABEL: name: test_f16.nearbyint
+ ; FP16: liveins: $h0
+ ; FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; FP16: [[FNEARBYINT:%[0-9]+]]:_(s16) = G_FNEARBYINT [[COPY]]
+ ; FP16: $h0 = COPY [[FNEARBYINT]](s16)
+ ; FP16: RET_ReallyLR implicit $h0
+ ; NO-FP16-LABEL: name: test_f16.nearbyint
+ ; NO-FP16: liveins: $h0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
+ ; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
+ ; NO-FP16: $h0 = COPY [[FPTRUNC]](s16)
+ ; NO-FP16: RET_ReallyLR implicit $h0
+ %0:_(s16) = COPY $h0
+ %1:_(s16) = G_FNEARBYINT %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=359204&r1=359203&r2=359204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Thu Apr 25 09:44:40 2019
@@ -352,7 +352,7 @@
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_FNEARBYINT (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
+# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
# CHECK-NOT: ill-defined
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir?rev=359204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir Thu Apr 25 09:44:40 2019
@@ -0,0 +1,158 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: test_v4f16.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4f16.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(<4 x s16>) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $d0 = COPY [[FNEARBYINT]](<4 x s16>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8f16.nearbyint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s16>) = COPY $q0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(<8 x s16>) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $q0 = COPY [[FNEARBYINT]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v2f32.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(<2 x s32>) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v2f64.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v2f64.nearbyint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(<2 x s64>) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(<2 x s64>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_f32.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: test_f32.nearbyint
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s32) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $s0 = COPY [[FNEARBYINT]](s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %1:_(s32) = G_FNEARBYINT %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_f64.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s64) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $d0 = COPY [[FNEARBYINT]](s64)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_FNEARBYINT %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_f16.nearbyint
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: test_f16.nearbyint
+ ; CHECK: liveins: $h0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s16) = COPY $h0
+ ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s16) = G_FNEARBYINT [[COPY]]
+ ; CHECK: $h0 = COPY [[FNEARBYINT]](s16)
+ ; CHECK: RET_ReallyLR implicit $h0
+ %0:_(s16) = COPY $h0
+ %1:_(s16) = G_FNEARBYINT %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir?rev=359204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir Thu Apr 25 09:44:40 2019
@@ -0,0 +1,165 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: test_v4f16.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4f16.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = FRINTIv4f16 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTIv4f16_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s16>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8f16.nearbyint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = FRINTIv8f16 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTIv8f16_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s16>) = COPY $q0
+ %1:fpr(<8 x s16>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v2f32.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = FRINTIv2f32 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTIv2f32_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s32>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v2f64.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v2f64.nearbyint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = FRINTIv2f64 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTIv2f64_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s64>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_f32.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: test_f32.nearbyint
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK: [[FRINTISr:%[0-9]+]]:fpr32 = FRINTISr [[COPY]]
+ ; CHECK: $s0 = COPY [[FRINTISr]]
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:fpr(s32) = COPY $s0
+ %1:fpr(s32) = G_FNEARBYINT %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_f64.nearbyint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTIDr:%[0-9]+]]:fpr64 = FRINTIDr [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTIDr]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(s64) = COPY $d0
+ %1:fpr(s64) = G_FNEARBYINT %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_f16.nearbyint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: test_f16.nearbyint
+ ; CHECK: liveins: $h0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+ ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = FRINTIHr [[COPY]]
+ ; CHECK: $h0 = COPY [[FRINTIHr]]
+ ; CHECK: RET_ReallyLR implicit $h0
+ %0:fpr(s16) = COPY $h0
+ %1:fpr(s16) = G_FNEARBYINT %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll?rev=359204&r1=359203&r2=359204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll Thu Apr 25 09:44:40 2019
@@ -215,12 +215,19 @@ define %v4f16 @test_v4f16.rint(%v4f16 %a
%1 = call %v4f16 @llvm.rint.v4f16(%v4f16 %a)
ret %v4f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v4f16.nearbyint
define %v4f16 @test_v4f16.nearbyint(%v4f16 %a) {
; CHECK-LABEL: test_v4f16.nearbyint:
; CHECK-NOFP16-COUNT-4: frinti s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frinti.4h
; CHECK-FP16-NEXT: ret
+ ; GISEL-LABEL: test_v4f16.nearbyint:
+ ; GISEL-NOFP16-COUNT-4: frinti s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frinti.4h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v4f16 @llvm.nearbyint.v4f16(%v4f16 %a)
ret %v4f16 %1
}
@@ -465,12 +472,19 @@ define %v8f16 @test_v8f16.rint(%v8f16 %a
%1 = call %v8f16 @llvm.rint.v8f16(%v8f16 %a)
ret %v8f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v8f16.nearbyint
define %v8f16 @test_v8f16.nearbyint(%v8f16 %a) {
; CHECK-LABEL: test_v8f16.nearbyint:
; CHECK-NOFP16-COUNT-8: frinti s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frinti.8h
; CHECK-FP16-NEXT: ret
+ ; GISEL-LABEL: test_v8f16.nearbyint:
+ ; GISEL-NOFP16-COUNT-8: frinti s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frinti.8h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v8f16 @llvm.nearbyint.v8f16(%v8f16 %a)
ret %v8f16 %1
}
@@ -657,9 +671,13 @@ define %v2f32 @test_v2f32.rint(%v2f32 %a
%1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
ret %v2f32 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v2f32.nearbyint
; CHECK-LABEL: test_v2f32.nearbyint:
+; GISEL-LABEL: test_v2f32.nearbyint:
define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
; CHECK: frinti.2s
+ ; GISEL: frinti.2s
%1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
ret %v2f32 %1
}
@@ -830,9 +848,13 @@ define %v4f32 @test_v4f32.rint(%v4f32 %a
%1 = call %v4f32 @llvm.rint.v4f32(%v4f32 %a)
ret %v4f32 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v4f32.nearbyint
; CHECK: test_v4f32.nearbyint:
+; GISEL: test_v4f32.nearbyint:
define %v4f32 @test_v4f32.nearbyint(%v4f32 %a) {
; CHECK: frinti.4s
+ ; GISEL: frinti.4s
%1 = call %v4f32 @llvm.nearbyint.v4f32(%v4f32 %a)
ret %v4f32 %1
}
@@ -1003,9 +1025,13 @@ define %v2f64 @test_v2f64.rint(%v2f64 %a
%1 = call %v2f64 @llvm.rint.v2f64(%v2f64 %a)
ret %v2f64 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v2f64.nearbyint
; CHECK: test_v2f64.nearbyint:
+; GISEL: test_v2f64.nearbyint:
define %v2f64 @test_v2f64.nearbyint(%v2f64 %a) {
; CHECK: frinti.2d
+ ; GISEL: frinti.2d
%1 = call %v2f64 @llvm.nearbyint.v2f64(%v2f64 %a)
ret %v2f64 %1
}
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