[PATCH] D61131: [AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, SjoerdMeijer.
Herald added subscribers: llvm-commits, psnobl, rkruppe, kristof.beyls, tschuett, javed.absar.
Herald added a project: LLVM.

This patch adds aliases for element sizes .B/.H/.S to the
AND/ORR/EOR/BIC bitwise logical instructions. The assembler now accepts
these instructions with all element sizes up to 64-bit (.D).  The
preferred disassembly is .D.


Repository:
  rL LLVM

https://reviews.llvm.org/D61131

Files:
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  lib/Target/AArch64/SVEInstrFormats.td
  test/MC/AArch64/SVE/and.s
  test/MC/AArch64/SVE/bic.s
  test/MC/AArch64/SVE/eor.s
  test/MC/AArch64/SVE/orr.s

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