[llvm] r359147 - [DAGCombiner] scale repeated FP divisor by splat factor
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 15:28:58 PDT 2019
Author: spatel
Date: Wed Apr 24 15:28:58 2019
New Revision: 359147
URL: http://llvm.org/viewvc/llvm-project?rev=359147&view=rev
Log:
[DAGCombiner] scale repeated FP divisor by splat factor
If we have a vector FP division with a splatted divisor, use the existing transform
that converts 'x/y' into 'x * (1.0/y)' to allow more conversions. This can then
potentially be converted into a scalar FP division by existing combines (rL358984)
as seen in the tests here.
That can be a potentially big perf difference if scalar fdiv has better timing
(including avoiding possible frequency throttling for vector ops).
Differential Revision: https://reviews.llvm.org/D61028
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/fdiv-combine-vec.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=359147&r1=359146&r2=359147&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 24 15:28:58 2019
@@ -11901,6 +11901,9 @@ SDValue DAGCombiner::visitFMA(SDNode *N)
// FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
// is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
+ // TODO: Limit this transform based on optsize/minsize - it always creates at
+ // least 1 extra instruction. But the perf win may be substantial enough
+ // that only minsize should restrict this.
bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath;
const SDNodeFlags Flags = N->getFlags();
if (!UnsafeMath && !Flags.hasAllowReciprocal())
@@ -11916,7 +11919,15 @@ SDValue DAGCombiner::combineRepeatedFPDi
// possibly be enough uses of the divisor to make the transform worthwhile.
SDValue N1 = N->getOperand(1);
unsigned MinUses = TLI.combineRepeatedFPDivisors();
- if (!MinUses || N1->use_size() < MinUses)
+
+ // For splat vectors, scale the number of uses by the splat factor. If we can
+ // convert the division into a scalar op, that will likely be much faster.
+ unsigned NumElts = 1;
+ EVT VT = N->getValueType(0);
+ if (VT.isVector() && DAG.isSplatValue(N1))
+ NumElts = VT.getVectorNumElements();
+
+ if (!MinUses || (N1->use_size() * NumElts) < MinUses)
return SDValue();
// Find all FDIV users of the same divisor.
@@ -11933,10 +11944,9 @@ SDValue DAGCombiner::combineRepeatedFPDi
// Now that we have the actual number of divisor uses, make sure it meets
// the minimum threshold specified by the target.
- if (Users.size() < MinUses)
+ if ((Users.size() * NumElts) < MinUses)
return SDValue();
- EVT VT = N->getValueType(0);
SDLoc DL(N);
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags);
Modified: llvm/trunk/test/CodeGen/X86/fdiv-combine-vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fdiv-combine-vec.ll?rev=359147&r1=359146&r2=359147&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fdiv-combine-vec.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fdiv-combine-vec.ll Wed Apr 24 15:28:58 2019
@@ -5,14 +5,18 @@
define <2 x double> @splat_fdiv_v2f64(<2 x double> %x, double %y) {
; SSE-LABEL: splat_fdiv_v2f64:
; SSE: # %bb.0:
-; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSE-NEXT: divpd %xmm1, %xmm0
+; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
+; SSE-NEXT: divsd %xmm1, %xmm2
+; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0,0]
+; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: splat_fdiv_v2f64:
; AVX: # %bb.0:
+; AVX-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
+; AVX-NEXT: vdivsd %xmm1, %xmm2, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
-; AVX-NEXT: vdivpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vy = insertelement <2 x double> undef, double %y, i32 0
%splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> zeroinitializer
@@ -32,9 +36,11 @@ define <4 x double> @splat_fdiv_v4f64(<4
;
; AVX-LABEL: splat_fdiv_v4f64:
; AVX: # %bb.0:
+; AVX-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
+; AVX-NEXT: vdivsd %xmm1, %xmm2, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vdivpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%vy = insertelement <4 x double> undef, double %y, i32 0
%splaty = shufflevector <4 x double> %vy, <4 x double> undef, <4 x i32> zeroinitializer
@@ -75,15 +81,11 @@ define <4 x float> @splat_fdiv_v4f32(<4
define <8 x float> @splat_fdiv_v8f32(<8 x float> %x, float %y) {
; SSE-LABEL: splat_fdiv_v8f32:
; SSE: # %bb.0:
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; SSE-NEXT: rcpps %xmm2, %xmm3
-; SSE-NEXT: mulps %xmm3, %xmm2
-; SSE-NEXT: movaps {{.*#+}} xmm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
-; SSE-NEXT: subps %xmm2, %xmm4
-; SSE-NEXT: mulps %xmm3, %xmm4
-; SSE-NEXT: addps %xmm3, %xmm4
-; SSE-NEXT: mulps %xmm4, %xmm0
-; SSE-NEXT: mulps %xmm4, %xmm1
+; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE-NEXT: divss %xmm2, %xmm3
+; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0,0,0]
+; SSE-NEXT: mulps %xmm3, %xmm0
+; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: splat_fdiv_v8f32:
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