[llvm] r359033 - [AArch64][GlobalISel] Legalize G_INTRINSIC_ROUND
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 14:11:57 PDT 2019
Author: paquette
Date: Tue Apr 23 14:11:57 2019
New Revision: 359033
URL: http://llvm.org/viewvc/llvm-project?rev=359033&view=rev
Log:
[AArch64][GlobalISel] Legalize G_INTRINSIC_ROUND
Add it to the same rule as G_FCEIL etc. Add a legalizer test, and add a missing
switch case to AArch64LegalizerInfo.cpp.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=359033&r1=359032&r2=359033&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Tue Apr 23 14:11:57 2019
@@ -1328,6 +1328,7 @@ LegalizerHelper::widenScalar(MachineInst
case TargetOpcode::G_FEXP2:
case TargetOpcode::G_FPOW:
case TargetOpcode::G_INTRINSIC_TRUNC:
+ case TargetOpcode::G_INTRINSIC_ROUND:
assert(TypeIdx == 0);
Observer.changingInstr(MI);
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=359033&r1=359032&r2=359033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Tue Apr 23 14:11:57 2019
@@ -130,8 +130,8 @@ AArch64LegalizerInfo::AArch64LegalizerIn
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
- getActionDefinitionsBuilder(
- {G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT, G_FMA, G_INTRINSIC_TRUNC})
+ getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
+ G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
.fewerElementsIf(
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir?rev=359033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir Tue Apr 23 14:11:57 2019
@@ -0,0 +1,272 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+
+# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
+# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
+
+...
+---
+name: test_f16.round
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; NO-FP16-LABEL: name: test_f16.round
+ ; NO-FP16: liveins: $h0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
+ ; NO-FP16: $h0 = COPY [[FPTRUNC]](s16)
+ ; NO-FP16: RET_ReallyLR implicit $h0
+ ; FP16-LABEL: name: test_f16.round
+ ; FP16: liveins: $h0
+ ; FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s16) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $h0 = COPY [[INTRINSIC_ROUND]](s16)
+ ; FP16: RET_ReallyLR implicit $h0
+ %0:_(s16) = COPY $h0
+ %1:_(s16) = G_INTRINSIC_ROUND %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: test_f32.round
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; NO-FP16-LABEL: name: test_f32.round
+ ; NO-FP16: liveins: $s0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[COPY]]
+ ; NO-FP16: $s0 = COPY [[INTRINSIC_ROUND]](s32)
+ ; NO-FP16: RET_ReallyLR implicit $s0
+ ; FP16-LABEL: name: test_f32.round
+ ; FP16: liveins: $s0
+ ; FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $s0 = COPY [[INTRINSIC_ROUND]](s32)
+ ; FP16: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %1:_(s32) = G_INTRINSIC_ROUND %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.round
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NO-FP16-LABEL: name: test_f64.round
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
+ ; NO-FP16: $d0 = COPY [[INTRINSIC_ROUND]](s64)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_f64.round
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $d0 = COPY [[INTRINSIC_ROUND]](s64)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.round
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NO-FP16-LABEL: name: test_v8f16.round
+ ; NO-FP16: liveins: $q0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT1]]
+ ; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND1]](s32)
+ ; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT2]]
+ ; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND2]](s32)
+ ; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND3:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT3]]
+ ; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND3]](s32)
+ ; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND4:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT4]]
+ ; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND4]](s32)
+ ; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND5:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT5]]
+ ; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND5]](s32)
+ ; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND6:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT6]]
+ ; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND6]](s32)
+ ; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND7:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT7]]
+ ; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND7]](s32)
+ ; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
+ ; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v8f16.round
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<8 x s16>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v4f16.round
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NO-FP16-LABEL: name: test_v4f16.round
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
+ ; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT1]]
+ ; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND1]](s32)
+ ; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT2]]
+ ; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND2]](s32)
+ ; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NO-FP16: [[INTRINSIC_ROUND3:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT3]]
+ ; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND3]](s32)
+ ; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
+ ; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_v4f16.round
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $d0 = COPY [[INTRINSIC_ROUND]](<4 x s16>)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v2f32.round
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NO-FP16-LABEL: name: test_v2f32.round
+ ; NO-FP16: liveins: $d0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
+ ; NO-FP16: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_v2f32.round
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v4f32.round
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NO-FP16-LABEL: name: test_v4f32.round
+ ; NO-FP16: liveins: $q0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
+ ; NO-FP16: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v4f32.round
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s32>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f64.round
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NO-FP16-LABEL: name: test_v2f64.round
+ ; NO-FP16: liveins: $q0
+ ; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
+ ; NO-FP16: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v2f64.round
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
+ ; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=359033&r1=359032&r2=359033&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Tue Apr 23 14:11:57 2019
@@ -91,7 +91,7 @@
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_INTRINSIC_ROUND (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
+# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_LOAD (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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