[PATCH] D61020: [ARM][ParallelDSP] Relax alias checks

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: SjoerdMeijer, dmgreen.
Herald added subscribers: kristof.beyls, javed.absar.

When deciding the safety of generating smlad, we checked for any writes within the block that may alias with any of the loads that need to be widened. This is overly conservative because it only matters when there's a potential aliasing write to a location accessed by a pair of loads.

Now we check for aliasing writes only once, during setup. If two loads are found to have an aliasing write between them, we don't add these loads to LoadPairs. This means that later during the transform, we can safely widened a pair without worrying about aliasing.

However, to maintain correctness, we also need to change the way that wide loads are inserted because the order is now important.

The MatchSMLAD method has also been changed, absorbing MatchReductions and AddMACCandidate to hopefully improve readability.


https://reviews.llvm.org/D61020

Files:
  lib/Target/ARM/ARMParallelDSP.cpp
  test/CodeGen/ARM/ParallelDSP/aliasing.ll
  test/CodeGen/ARM/ParallelDSP/smlad0.ll
  test/CodeGen/ARM/ParallelDSP/smlad1.ll
  test/CodeGen/ARM/ParallelDSP/smlad11.ll
  test/CodeGen/ARM/ParallelDSP/smlad6.ll
  test/CodeGen/ARM/ParallelDSP/smlad7.ll
  test/CodeGen/ARM/ParallelDSP/smladx-1.ll
  test/CodeGen/ARM/ParallelDSP/smlald0.ll
  test/CodeGen/ARM/ParallelDSP/smlald1.ll
  test/CodeGen/ARM/ParallelDSP/smlald2.ll
  test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll
  test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll

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