[llvm] r358987 - ARM: disallow add/sub to sp unless Rn is also sp.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 06:50:14 PDT 2019
Author: tnorthover
Date: Tue Apr 23 06:50:13 2019
New Revision: 358987
URL: http://llvm.org/viewvc/llvm-project?rev=358987&view=rev
Log:
ARM: disallow add/sub to sp unless Rn is also sp.
The manual says that Thumb2 add/sub instructions are only allowed to modify sp
if the first source is also sp. This is slightly different from the usual rGPR
restriction since it's context-sensitive, so implement it in C++.
Added:
llvm/trunk/test/MC/ARM/invalid-addsub.s
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=358987&r1=358986&r2=358987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Apr 23 06:50:13 2019
@@ -6792,6 +6792,20 @@ bool ARMAsmParser::validateInstruction(M
}
break;
+ case ARM::t2ADDri:
+ case ARM::t2ADDri12:
+ case ARM::t2ADDrr:
+ case ARM::t2ADDrs:
+ case ARM::t2SUBri:
+ case ARM::t2SUBri12:
+ case ARM::t2SUBrr:
+ case ARM::t2SUBrs:
+ if (Inst.getOperand(0).getReg() == ARM::SP &&
+ Inst.getOperand(1).getReg() != ARM::SP)
+ return Error(Operands[4]->getStartLoc(),
+ "source register must be sp if destination is sp");
+ break;
+
// Final range checking for Thumb unconditional branch instructions.
case ARM::tB:
if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=358987&r1=358986&r2=358987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Apr 23 06:50:13 2019
@@ -441,6 +441,18 @@ static DecodeStatus checkDecodedInstruct
return MCDisassembler::SoftFail;
return Result;
}
+ case ARM::t2ADDri:
+ case ARM::t2ADDri12:
+ case ARM::t2ADDrr:
+ case ARM::t2ADDrs:
+ case ARM::t2SUBri:
+ case ARM::t2SUBri12:
+ case ARM::t2SUBrr:
+ case ARM::t2SUBrs:
+ if (MI.getOperand(0).getReg() == ARM::SP &&
+ MI.getOperand(1).getReg() != ARM::SP)
+ return MCDisassembler::SoftFail;
+ return Result;
default: return Result;
}
}
@@ -772,7 +784,7 @@ DecodeStatus ThumbDisassembler::getInstr
if (Result != MCDisassembler::Fail) {
Size = 4;
Check(Result, AddThumbPredicate(MI));
- return Result;
+ return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result);
}
if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Added: llvm/trunk/test/MC/ARM/invalid-addsub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/invalid-addsub.s?rev=358987&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/invalid-addsub.s (added)
+++ llvm/trunk/test/MC/ARM/invalid-addsub.s Tue Apr 23 06:50:13 2019
@@ -0,0 +1,20 @@
+@ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o - 2>&1 | FileCheck %s
+
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+add sp, r5, #1
+addw sp, r7, #4
+add sp, r3, r2
+add sp, r3, r5, lsl #3
+
+
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+@ CHECK: error: source register must be sp if destination is sp
+sub sp, r5, #1
+subw sp, r7, #4
+sub sp, r3, r2
+sub sp, r3, r5, lsl #3
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt?rev=358987&r1=358986&r2=358987&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt Tue Apr 23 06:50:13 2019
@@ -394,3 +394,34 @@
[0xff,0xf3,0x30,0x80]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0xff,0xf3,0x30,0x80]
+
+#------------------------------------------------------------------------------
+# If dest is sp then source must be in T2 add/sub
+#------------------------------------------------------------------------------
+
+[0x05,0xf1,0x01,0x0d]
+[0x07,0xf2,0x04,0x0d]
+[0x03,0xeb,0x02,0x0d]
+[0x03,0xeb,0xc5,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x05,0xf1,0x01,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x07,0xf2,0x04,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x03,0xeb,0x02,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x03,0xeb,0xc5,0x0d]
+
+
+[0xa5,0xf1,0x01,0x0d]
+[0xa7,0xf2,0x04,0x0d]
+[0xa3,0xeb,0x02,0x0d]
+[0xa3,0xeb,0xc5,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0xa5,0xf1,0x01,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0xa7,0xf2,0x04,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0xa3,0xeb,0x02,0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0xa3,0xeb,0xc5,0x0d]
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