[llvm] r358969 - Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Apr 23 04:11:34 2019
New Revision: 358969

URL: http://llvm.org/viewvc/llvm-project?rev=358969&view=rev
Log:
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=358969&r1=358968&r2=358969&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Tue Apr 23 04:11:34 2019
@@ -710,7 +710,7 @@ bool AArch64DAGToDAGISel::SelectAddrMode
       if (IsSignedImm) {
         int64_t RHSC = RHS->getSExtValue();
         unsigned Scale = Log2_32(Size);
-        int64_t Range = 0x1 << (BW-1);
+        int64_t Range = 0x1LL << (BW - 1);
 
         if ((RHSC & (Size - 1)) == 0 && RHSC >= -(Range << Scale) &&
             RHSC < (Range << Scale)) {
@@ -726,7 +726,7 @@ bool AArch64DAGToDAGISel::SelectAddrMode
         // unsigned Immediate
         uint64_t RHSC = RHS->getZExtValue();
         unsigned Scale = Log2_32(Size);
-        uint64_t Range = 0x1 << BW;
+        uint64_t Range = 0x1ULL << BW;
 
         if ((RHSC & (Size - 1)) == 0 && RHSC < (Range << Scale)) {
           Base = N.getOperand(0);