[llvm] r358799 - [GlobalISel][AArch64] Legalize + select G_FRINT
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 19 16:41:53 PDT 2019
Author: paquette
Date: Fri Apr 19 16:41:52 2019
New Revision: 358799
URL: http://llvm.org/viewvc/llvm-project?rev=358799&view=rev
Log:
[GlobalISel][AArch64] Legalize + select G_FRINT
Exactly the same as G_FCEIL, G_FABS, etc.
Add tests for the fp16/nofp16 behaviour, update arm64-vfloatintrinsics, etc.
Differential Revision: https://reviews.llvm.org/D60895
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=358799&r1=358798&r2=358799&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Fri Apr 19 16:41:52 2019
@@ -1315,6 +1315,7 @@ LegalizerHelper::widenScalar(MachineInst
case TargetOpcode::G_FLOG10:
case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2:
+ case TargetOpcode::G_FRINT:
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FEXP:
case TargetOpcode::G_FEXP2:
@@ -2183,6 +2184,7 @@ LegalizerHelper::fewerElementsVector(Mac
case G_FLOG10:
case G_FCEIL:
case G_FFLOOR:
+ case G_FRINT:
case G_INTRINSIC_ROUND:
case G_INTRINSIC_TRUNC:
case G_FCOS:
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=358799&r1=358798&r2=358799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Fri Apr 19 16:41:52 2019
@@ -130,7 +130,7 @@ AArch64LegalizerInfo::AArch64LegalizerIn
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
- getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR})
+ getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
.fewerElementsIf(
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=358799&r1=358798&r2=358799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Apr 19 16:41:52 2019
@@ -404,6 +404,7 @@ static bool isPreISelGenericFloatingPoin
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FABS:
case TargetOpcode::G_FEXP:
+ case TargetOpcode::G_FRINT:
return true;
}
return false;
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir?rev=358799&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir Fri Apr 19 16:41:52 2019
@@ -0,0 +1,245 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s --check-prefix=NOFP16
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s --check-prefix=FP16
+
+name: test_f16.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ %0:_(s16) = COPY $h0
+ %1:_(s16) = G_FRINT %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: test_f32.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; NOFP16-LABEL: name: test_f32.rint
+ ; NOFP16: liveins: $s0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
+ ; NOFP16: $s0 = COPY [[FRINT]](s32)
+ ; NOFP16: RET_ReallyLR implicit $s0
+ ; FP16-LABEL: name: test_f32.rint
+ ; FP16: liveins: $s0
+ ; FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; FP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
+ ; FP16: $s0 = COPY [[FRINT]](s32)
+ ; FP16: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %1:_(s32) = G_FRINT %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NOFP16-LABEL: name: test_f64.rint
+ ; NOFP16: liveins: $d0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
+ ; NOFP16: $d0 = COPY [[FRINT]](s64)
+ ; NOFP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_f64.rint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; FP16: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
+ ; FP16: $d0 = COPY [[FRINT]](s64)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_FRINT %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v4f32.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NOFP16-LABEL: name: test_v4f32.rint
+ ; NOFP16: liveins: $q0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(<4 x s32>) = G_FRINT [[COPY]]
+ ; NOFP16: $q0 = COPY [[FRINT]](<4 x s32>)
+ ; NOFP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v4f32.rint
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; FP16: [[FRINT:%[0-9]+]]:_(<4 x s32>) = G_FRINT [[COPY]]
+ ; FP16: $q0 = COPY [[FRINT]](<4 x s32>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s32>) = G_FRINT %0
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f64.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NOFP16-LABEL: name: test_v2f64.rint
+ ; NOFP16: liveins: $q0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(<2 x s64>) = G_FRINT [[COPY]]
+ ; NOFP16: $q0 = COPY [[FRINT]](<2 x s64>)
+ ; NOFP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v2f64.rint
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; FP16: [[FRINT:%[0-9]+]]:_(<2 x s64>) = G_FRINT [[COPY]]
+ ; FP16: $q0 = COPY [[FRINT]](<2 x s64>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(<2 x s64>) = G_FRINT %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v4f16.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NOFP16-LABEL: name: test_v4f16.rint
+ ; NOFP16: liveins: $d0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; NOFP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; NOFP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
+ ; NOFP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
+ ; NOFP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NOFP16: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT1]]
+ ; NOFP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT1]](s32)
+ ; NOFP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NOFP16: [[FRINT2:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT2]]
+ ; NOFP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT2]](s32)
+ ; NOFP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NOFP16: [[FRINT3:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT3]]
+ ; NOFP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT3]](s32)
+ ; NOFP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
+ ; NOFP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; NOFP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_v4f16.rint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; FP16: [[FRINT:%[0-9]+]]:_(<4 x s16>) = G_FRINT [[COPY]]
+ ; FP16: $d0 = COPY [[FRINT]](<4 x s16>)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = G_FRINT %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; NOFP16-LABEL: name: test_v8f16.rint
+ ; NOFP16: liveins: $q0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; NOFP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; NOFP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
+ ; NOFP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
+ ; NOFP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; NOFP16: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT1]]
+ ; NOFP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT1]](s32)
+ ; NOFP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; NOFP16: [[FRINT2:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT2]]
+ ; NOFP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT2]](s32)
+ ; NOFP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; NOFP16: [[FRINT3:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT3]]
+ ; NOFP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT3]](s32)
+ ; NOFP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
+ ; NOFP16: [[FRINT4:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT4]]
+ ; NOFP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT4]](s32)
+ ; NOFP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
+ ; NOFP16: [[FRINT5:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT5]]
+ ; NOFP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT5]](s32)
+ ; NOFP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
+ ; NOFP16: [[FRINT6:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT6]]
+ ; NOFP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT6]](s32)
+ ; NOFP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
+ ; NOFP16: [[FRINT7:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT7]]
+ ; NOFP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT7]](s32)
+ ; NOFP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
+ ; NOFP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
+ ; NOFP16: RET_ReallyLR implicit $q0
+ ; FP16-LABEL: name: test_v8f16.rint
+ ; FP16: liveins: $q0
+ ; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; FP16: [[FRINT:%[0-9]+]]:_(<8 x s16>) = G_FRINT [[COPY]]
+ ; FP16: $q0 = COPY [[FRINT]](<8 x s16>)
+ ; FP16: RET_ReallyLR implicit $q0
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = G_FRINT %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.rint
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; NOFP16-LABEL: name: test_v2f32.rint
+ ; NOFP16: liveins: $d0
+ ; NOFP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; NOFP16: [[FRINT:%[0-9]+]]:_(<2 x s32>) = G_FRINT [[COPY]]
+ ; NOFP16: $d0 = COPY [[FRINT]](<2 x s32>)
+ ; NOFP16: RET_ReallyLR implicit $d0
+ ; FP16-LABEL: name: test_v2f32.rint
+ ; FP16: liveins: $d0
+ ; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; FP16: [[FRINT:%[0-9]+]]:_(<2 x s32>) = G_FRINT [[COPY]]
+ ; FP16: $d0 = COPY [[FRINT]](<2 x s32>)
+ ; FP16: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = G_FRINT %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=358799&r1=358798&r2=358799&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Fri Apr 19 16:41:52 2019
@@ -349,7 +349,7 @@
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_FRINT (opcode 146): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
+# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
# CHECK-NOT: ill-defined
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir?rev=358799&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir Fri Apr 19 16:41:52 2019
@@ -0,0 +1,200 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s
+
+...
+---
+name: test_f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: test_f16.rint
+ ; CHECK: liveins: $h0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+ ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
+ ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
+ ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
+ ; CHECK: $h0 = COPY [[FCVTHSr]]
+ ; CHECK: RET_ReallyLR implicit $h0
+ %0:fpr(s16) = COPY $h0
+ %2:fpr(s32) = G_FPEXT %0(s16)
+ %3:fpr(s32) = G_FRINT %2
+ %1:fpr(s16) = G_FPTRUNC %3(s32)
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: test_v4f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4f16.rint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
+ ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
+ ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
+ ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
+ ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2
+ ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3
+ ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
+ ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
+ ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
+ ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]]
+ ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
+ ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
+ ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]]
+ ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
+ ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
+ ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]]
+ ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
+ ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
+ ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub
+ ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub
+ ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
+ ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub
+ ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
+ ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub
+ ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
+ ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
+ ; CHECK: $d0 = COPY [[COPY2]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
+ %16:fpr(s32) = G_FPEXT %2(s16)
+ %17:fpr(s32) = G_FRINT %16
+ %6:fpr(s16) = G_FPTRUNC %17(s32)
+ %14:fpr(s32) = G_FPEXT %3(s16)
+ %15:fpr(s32) = G_FRINT %14
+ %7:fpr(s16) = G_FPTRUNC %15(s32)
+ %12:fpr(s32) = G_FPEXT %4(s16)
+ %13:fpr(s32) = G_FRINT %12
+ %8:fpr(s16) = G_FPTRUNC %13(s32)
+ %10:fpr(s32) = G_FPEXT %5(s16)
+ %11:fpr(s32) = G_FRINT %10
+ %9:fpr(s16) = G_FPTRUNC %11(s32)
+ %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8f16.rint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
+ ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
+ ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2
+ ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3
+ ; CHECK: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4
+ ; CHECK: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5
+ ; CHECK: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6
+ ; CHECK: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7
+ ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
+ ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
+ ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
+ ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]]
+ ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
+ ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
+ ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]]
+ ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
+ ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
+ ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]]
+ ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
+ ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
+ ; CHECK: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_3]]
+ ; CHECK: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]]
+ ; CHECK: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]]
+ ; CHECK: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_4]]
+ ; CHECK: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]]
+ ; CHECK: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]]
+ ; CHECK: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_5]]
+ ; CHECK: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]]
+ ; CHECK: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]]
+ ; CHECK: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_6]]
+ ; CHECK: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]]
+ ; CHECK: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]]
+ ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub
+ ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub
+ ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
+ ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub
+ ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
+ ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub
+ ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
+ ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub
+ ; CHECK: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
+ ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub
+ ; CHECK: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
+ ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub
+ ; CHECK: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
+ ; CHECK: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub
+ ; CHECK: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
+ ; CHECK: $q0 = COPY [[INSvi16lane6]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s16>) = COPY $q0
+ %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
+ %32:fpr(s32) = G_FPEXT %2(s16)
+ %33:fpr(s32) = G_FRINT %32
+ %10:fpr(s16) = G_FPTRUNC %33(s32)
+ %30:fpr(s32) = G_FPEXT %3(s16)
+ %31:fpr(s32) = G_FRINT %30
+ %11:fpr(s16) = G_FPTRUNC %31(s32)
+ %28:fpr(s32) = G_FPEXT %4(s16)
+ %29:fpr(s32) = G_FRINT %28
+ %12:fpr(s16) = G_FPTRUNC %29(s32)
+ %26:fpr(s32) = G_FPEXT %5(s16)
+ %27:fpr(s32) = G_FRINT %26
+ %13:fpr(s16) = G_FPTRUNC %27(s32)
+ %24:fpr(s32) = G_FPEXT %6(s16)
+ %25:fpr(s32) = G_FRINT %24
+ %14:fpr(s16) = G_FPTRUNC %25(s32)
+ %22:fpr(s32) = G_FPEXT %7(s16)
+ %23:fpr(s32) = G_FRINT %22
+ %15:fpr(s16) = G_FPTRUNC %23(s32)
+ %20:fpr(s32) = G_FPEXT %8(s16)
+ %21:fpr(s32) = G_FRINT %20
+ %16:fpr(s16) = G_FPTRUNC %21(s32)
+ %18:fpr(s32) = G_FPEXT %9(s16)
+ %19:fpr(s32) = G_FRINT %18
+ %17:fpr(s16) = G_FPTRUNC %19(s32)
+ %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir?rev=358799&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir Fri Apr 19 16:41:52 2019
@@ -0,0 +1,188 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s
+
+...
+---
+name: test_f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: test_f16.rint
+ ; CHECK: liveins: $h0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+ ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = FRINTXHr [[COPY]]
+ ; CHECK: $h0 = COPY [[FRINTXHr]]
+ ; CHECK: RET_ReallyLR implicit $h0
+ %0:fpr(s16) = COPY $h0
+ %1:fpr(s16) = G_FRINT %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: test_f32.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: test_f32.rint
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[COPY]]
+ ; CHECK: $s0 = COPY [[FRINTXSr]]
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:fpr(s32) = COPY $s0
+ %1:fpr(s32) = G_FRINT %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f64.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_f64.rint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = FRINTXDr [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTXDr]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(s64) = COPY $d0
+ %1:fpr(s64) = G_FRINT %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v4f32.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v4f32.rint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = FRINTXv4f32 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTXv4f32_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:fpr(<4 x s32>) = G_FRINT %0
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f64.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v2f64.rint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = FRINTXv2f64 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTXv2f64_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s64>) = G_FRINT %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v4f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4f16.rint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = FRINTXv4f16 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTXv4f16_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s16>) = G_FRINT %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8f16.rint
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = FRINTXv8f16 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTXv8f16_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s16>) = COPY $q0
+ %1:fpr(<8 x s16>) = G_FRINT %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.rint
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v2f32.rint
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = FRINTXv2f32 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTXv2f32_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s32>) = G_FRINT %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll?rev=358799&r1=358798&r2=358799&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll Fri Apr 19 16:41:52 2019
@@ -186,12 +186,19 @@ define %v4f16 @test_v4f16.trunc(%v4f16 %
%1 = call %v4f16 @llvm.trunc.v4f16(%v4f16 %a)
ret %v4f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v4f16.rint
define %v4f16 @test_v4f16.rint(%v4f16 %a) {
; CHECK-LABEL: test_v4f16.rint:
; CHECK-NOFP16-COUNT-4: frintx s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frintx.4h
; CHECK-FP16-NEXT: ret
+ ; GISEL-LABEL: test_v4f16.rint:
+ ; GISEL-NOFP16-COUNT-4: frintx s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frintx.4h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v4f16 @llvm.rint.v4f16(%v4f16 %a)
ret %v4f16 %1
}
@@ -411,12 +418,19 @@ define %v8f16 @test_v8f16.trunc(%v8f16 %
%1 = call %v8f16 @llvm.trunc.v8f16(%v8f16 %a)
ret %v8f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v8f16.rint
define %v8f16 @test_v8f16.rint(%v8f16 %a) {
; CHECK-LABEL: test_v8f16.rint:
; CHECK-NOFP16-COUNT-8: frintx s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frintx.8h
; CHECK-FP16-NEXT: ret
+ ; GISEL-LABEL: test_v8f16.rint:
+ ; GISEL-NOFP16-COUNT-8: frintx s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frintx.8h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v8f16 @llvm.rint.v8f16(%v8f16 %a)
ret %v8f16 %1
}
@@ -592,8 +606,11 @@ define %v2f32 @test_v2f32.trunc(%v2f32 %
ret %v2f32 %1
}
; CHECK-LABEL: test_v2f32.rint:
+; FALLBACK-NOT: remark{{.*}}test_v2f32.rint
+; GISEL-LABEL: test_v2f32.rint:
define %v2f32 @test_v2f32.rint(%v2f32 %a) {
; CHECK: frintx.2s
+ ; GISEL: frintx.2s
%1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
ret %v2f32 %1
}
@@ -755,8 +772,11 @@ define %v4f32 @test_v4f32.trunc(%v4f32 %
ret %v4f32 %1
}
; CHECK: test_v4f32.rint:
+; FALLBACK-NOT: remark{{.*}}test_v4f32.rint
+; GISEL: test_v4f32.rint:
define %v4f32 @test_v4f32.rint(%v4f32 %a) {
; CHECK: frintx.4s
+ ; GISEL: frintx.4s
%1 = call %v4f32 @llvm.rint.v4f32(%v4f32 %a)
ret %v4f32 %1
}
@@ -918,8 +938,11 @@ define %v2f64 @test_v2f64.trunc(%v2f64 %
ret %v2f64 %1
}
; CHECK: test_v2f64.rint:
+; FALLBACK-NOT: remark{{.*}}test_v2f64.rint
+; GISEL: test_v2f64.rint:
define %v2f64 @test_v2f64.rint(%v2f64 %a) {
; CHECK: frintx.2d
+ ; GISEL: frintx.2d
%1 = call %v2f64 @llvm.rint.v2f64(%v2f64 %a)
ret %v2f64 %1
}
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