[PATCH] D60877: [GlobalISel][AArch64] Legalize v8s8 loads

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

Add legalizer support for loads of v8s8 and update legalize-load-store.mir.


https://reviews.llvm.org/D60877

Files:
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -48,6 +48,11 @@
     ret <16 x i8> %res
   }
 
+  define <8 x i8> @load_8xi8(<8 x i8>* %ptr) {
+    %res = load <8 x i8>, <8 x i8>* %ptr
+    ret <8 x i8> %res
+  }
+
 ...
 ---
 name:            test_load
@@ -319,3 +324,23 @@
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            load_8xi8
+alignment:       2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $x0
+    ; CHECK-LABEL: name: load_8xi8
+    ; CHECK: liveins: $x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
+    ; CHECK: $d0 = COPY [[LOAD]](<8 x s8>)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(p0) = COPY $x0
+    %1:_(<8 x s8>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
+    $d0 = COPY %1(<8 x s8>)
+    RET_ReallyLR implicit $d0
+
+...
Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -224,6 +224,7 @@
                                  {s32, p0, 32, 8},
                                  {s64, p0, 64, 8},
                                  {p0, p0, 64, 8},
+                                 {v8s8, p0, 64, 8},
                                  {v16s8, p0, 128, 8},
                                  {v4s16, p0, 64, 8},
                                  {v8s16, p0, 128, 8},


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