[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added subscribers: rampitec, arsenm.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM (see inline for a couple of nits) - but I'd prefer that someone with AMDGPU knowledge (@arsenm @nhaehnle @rampitec ?) confirm those diffs too.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2106
 
-SDValue DAGCombiner::visitADD(SDNode *N) {
+/// Try to fold a node that behaves like an ADD (note that N isn't neccessarily
+/// an ISD::ADD here, it could for example be an ISD::OR if we known that there
----------------
typo: necessarily


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2107
+/// Try to fold a node that behaves like an ADD (note that N isn't neccessarily
+/// an ISD::ADD here, it could for example be an ISD::OR if we known that there
+/// are no common bits set in the operands).
----------------
typo: known -> know


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https://reviews.llvm.org/D59758