[PATCH] D60854: [DAGLegalize][PowerPC] Add promote legalization of addc/adde and subc/sube

[Zixuan Wu via Phabricator via llvm-commits]

wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai, jsji, eli.friedman.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

https://bugs.llvm.org/show_bug.cgi?id=40922

Promote operand type of add/adde and subc/sube by signed extending them and keep the carry bit state of original type

I found it's hard to add test cases for other targets rather than POWER because i1 is not legal register type on other target,
which is that i1 type is legalized before legalization DAG phase in type legalization phase.


Repository:
  rL LLVM

https://reviews.llvm.org/D60854

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pr40922.ll


Index: llvm/test/CodeGen/PowerPC/pr40922.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr40922.ll
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s
+
+; Test case adapted from PR40922.
+
+ at a.b = internal global i32 0, align 4
+
+define i32 @a() {
+entry:
+  %call = tail call i32 bitcast (i32 (...)* @d to i32 ()*)()
+  %0 = load i32, i32* @a.b, align 4
+  %conv = zext i32 %0 to i64
+  %add = add nuw nsw i64 %conv, 6
+  %and = and i64 %add, 8589934575
+  %cmp = icmp ult i64 %and, %conv
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %call3 = tail call i32 bitcast (i32 (...)* @e to i32 ()*)()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  store i32 %call, i32* @a.b, align 4
+  ret i32 undef
+}
+
+declare i32 @d(...)
+
+declare i32 @e(...)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -192,6 +192,16 @@
   if (Subtarget.useCRBits()) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
+    setOperationAction(ISD::ADDC, MVT::i1, Promote);
+    AddPromotedToType(ISD::ADDC, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32);
+    setOperationAction(ISD::SUBC, MVT::i1, Promote);
+    AddPromotedToType(ISD::SUBC, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32);
+
+    setOperationAction(ISD::ADDE, MVT::i1, Promote);
+    AddPromotedToType(ISD::ADDE, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32);
+    setOperationAction(ISD::SUBE, MVT::i1, Promote);
+    AddPromotedToType(ISD::SUBE, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32);
+
     if (isPPC64 || Subtarget.hasFPCVT()) {
       setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
       AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4046,6 +4046,25 @@
     }
     Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
     break;
+  case ISD::SUBC:
+  case ISD::SUBE:
+  case ISD::ADDC:
+  case ISD::ADDE: {
+    Tmp1 = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
+    Tmp2 = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(1));
+
+    SmallVector<SDValue, 4> Ops = {Tmp1, Tmp2};
+    if (Node->getOpcode() == ISD::ADDE || Node->getOpcode() == ISD::SUBE)
+      Ops.push_back(Node->getOperand(2));
+
+    Tmp3 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Glue}, Ops);
+    SDValue Res = DAG.getNode(ISD::TRUNCATE, dl, {OVT, MVT::Glue},
+                              {Tmp3, Tmp3.getValue(1)});
+
+    Results.push_back(Res);
+    Results.push_back(Res.getValue(1));
+    break;
+  }
   case ISD::BITREVERSE:
   case ISD::BSWAP: {
     unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();


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