[llvm] r358603 - [AsmPrinter] defer %c to base class for ARM, PPC, and Hexagon. NFC
Nick Desaulniers via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 11:22:48 PDT 2019
Author: nickdesaulniers
Date: Wed Apr 17 11:22:48 2019
New Revision: 358603
URL: http://llvm.org/viewvc/llvm-project?rev=358603&view=rev
Log:
[AsmPrinter] defer %c to base class for ARM, PPC, and Hexagon. NFC
Summary:
None of these derived classes do anything that the base class cannot.
If we remove these case statements, then the base class can handle them
just fine.
Reviewers: peter.smith, echristo
Reviewed By: echristo
Subscribers: nemanjai, javed.absar, eraman, kristof.beyls, hiraditya, kbarton, jsji, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60803
Added:
llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll
llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll
llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=358603&r1=358602&r2=358603&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Wed Apr 17 11:22:48 2019
@@ -425,6 +425,8 @@ static void EmitGCCInlineAsmStr(const ch
unsigned OpFlags = MI->getOperand(OpNo).getImm();
++OpNo; // Skip over the ID number.
+ // FIXME: Shouldn't arch-independant output template handling go into
+ // PrintAsmOperand?
if (Modifier[0] == 'l') { // Labels are target independent.
if (MI->getOperand(OpNo).isBlockAddress()) {
const BlockAddress *BA = MI->getOperand(OpNo).getBlockAddress();
@@ -606,6 +608,7 @@ bool AsmPrinter::PrintAsmOperand(const M
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true; // Unknown modifier.
+ // https://gcc.gnu.org/onlinedocs/gccint/Output-Template.html
const MachineOperand &MO = MI->getOperand(OpNo);
switch (ExtraCode[0]) {
default:
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=358603&r1=358602&r2=358603&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Apr 17 11:22:48 2019
@@ -270,13 +270,11 @@ bool ARMAsmPrinter::PrintAsmOperand(cons
<< ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
<< "]";
return false;
+ } else if (MI->getOperand(OpNum).isImm()) {
+ O << MI->getOperand(OpNum).getImm();
+ return false;
}
- LLVM_FALLTHROUGH;
- case 'c': // Don't print "#" before an immediate operand.
- if (!MI->getOperand(OpNum).isImm())
- return true;
- O << MI->getOperand(OpNum).getImm();
- return false;
+ return true;
case 'P': // Print a VFP double precision register.
case 'q': // Print a NEON quad precision register.
printOperand(MI, OpNum, O);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=358603&r1=358602&r2=358603&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Wed Apr 17 11:22:48 2019
@@ -124,10 +124,6 @@ bool HexagonAsmPrinter::PrintAsmOperand(
default:
// See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
- case 'c': // Don't print "$" before a global var name or constant.
- // Hexagon never has a prefix.
- printOperand(MI, OpNo, OS);
- return false;
case 'L':
case 'H': { // The highest-numbered register of a pair.
const MachineOperand &MO = MI->getOperand(OpNo);
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=358603&r1=358602&r2=358603&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Apr 17 11:22:48 2019
@@ -231,8 +231,6 @@ bool PPCAsmPrinter::PrintAsmOperand(cons
default:
// See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
- case 'c': // Don't print "$" before a global var name or constant.
- break; // PPC never has a prefix.
case 'L': // Write second word of DImode reference.
// Verify that this operand has two consecutive registers.
if (!MI->getOperand(OpNo).isReg() ||
Added: llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll?rev=358603&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll Wed Apr 17 11:22:48 2019
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=armv7-linux-gnueabi < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: @TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+ tail call void asm sideeffect "@TEST ${0:c}", "i"(i32 42)
+ ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: @TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+ tail call void asm sideeffect "@TEST ${0:n}", "i"(i32 42)
+ ret i32 42
+}
Added: llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll?rev=358603&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll Wed Apr 17 11:22:48 2019
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: //TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+ tail call void asm sideeffect "//TEST ${0:c}", "i"(i32 42)
+ ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: //TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+ tail call void asm sideeffect "//TEST ${0:n}", "i"(i32 42)
+ ret i32 42
+}
Added: llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll?rev=358603&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll Wed Apr 17 11:22:48 2019
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=ppc32-- < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+ tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+ ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+ tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+ ret i32 42
+}
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