[PATCH] D60462: [TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a reviewer: nhaehnle.
RKSimon added inline comments.


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Comment at: test/CodeGen/AMDGPU/store-weird-sizes.ll:49
+; HAWAII-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; HAWAII-NEXT:    v_bfe_u32 v0, v0, 16, 7
 ; HAWAII-NEXT:    ds_write_b8 v1, v0 offset:6
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nhaehnle wrote:
> RKSimon wrote:
> > @arsenm Any suggestions on what to do here - is it better to add another isel pattern or start creating bfe_user dag nodes?
> Why doesn't the DAGCombiner simplify this to a single AND node?
The AND appears too late (from a bitcasted i64 -> v2i32) for visitShiftByConstant to be called from the SRL node - I'm working on a generic fix at the moment.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D60462/new/

https://reviews.llvm.org/D60462