[PATCH] D60640: AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:69-74
+  auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
+  const TargetRegisterClass *RC =
+      RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
+  if (RC)
+    return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
+           MRI.getType(Reg).getSizeInBits() == 1;
----------------
This should not happen? There should be no 1-bit SReg_32_XM0RegClassID registers


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:86-87
+
+  // Special case for COPY from the scc register bank.  The scc register bank
+  // is modeled using 32-bit sgprs.
+  const MachineOperand &Src = I.getOperand(1);
----------------
This isn't true, or at least isn't supposed to be. The SCC bank needs to be distinct from a 1-bit value in an SGPR bank


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60640/new/

https://reviews.llvm.org/D60640