[PATCH] D60314: [DAGCombiner] Add missing flag to addressing mode check

[Luís Marques via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL358502: [DAGCombiner] Add missing flag to addressing mode check (authored by luismarques, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D60314?vs=193851&id=195387#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60314/new/

https://reviews.llvm.org/D60314

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12897,6 +12897,7 @@
 
   TargetLowering::AddrMode AM;
   if (N->getOpcode() == ISD::ADD) {
+    AM.HasBaseReg = true;
     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]
@@ -12905,6 +12906,7 @@
       // [reg +/- reg]
       AM.Scale = 1;
   } else if (N->getOpcode() == ISD::SUB) {
+    AM.HasBaseReg = true;
     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]


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