[PATCH] D60701: [ARM] add new LLVM addressing modes for v8.1-M and MVE.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

There's a new mode for the BF instruction, and another three for MVE
vector loads, which take a 7-bit immediate offset scaled by 1, 2 or 4.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60701

Files:
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp


Index: llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -610,9 +610,22 @@
         Offset = -Offset;
         isSub = true;
       }
+    } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
+               AddrMode == ARMII::AddrModeT2_i7s2 ||
+               AddrMode == ARMII::AddrModeT2_i7) {
+      Offset += MI.getOperand(FrameRegIdx + 1).getImm();
+      NumBits = 7;
+      unsigned OffsetMask = 0x0;
+      switch (AddrMode) {
+      case ARMII::AddrModeT2_i7s4: NumBits += 2; OffsetMask = 0x3; break;
+      case ARMII::AddrModeT2_i7s2: NumBits += 1; OffsetMask = 0x1; break;
+      }
+      // MCInst operand expects already scaled value.
+      Scale = 1;
+      assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
-      NumBits = 10; // 8 bits scaled by 4
+      NumBits = 8 + 2;
       // MCInst operand expects already scaled value.
       Scale = 1;
       assert((Offset & 3) == 0 && "Can't encode this offset!");
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
===================================================================
--- llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
@@ -202,6 +202,10 @@
     AddrMode_i12    = 16,
     AddrMode5FP16   = 17,  // i8 * 2
     AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
+    AddrMode_bf     = 19,
+    AddrModeT2_i7s4 = 20, // i7 * 4
+    AddrModeT2_i7s2 = 21, // i7 * 2
+    AddrModeT2_i7   = 22, // i7 * 1
   };
 
   inline static const char *AddrModeToString(AddrMode addrmode) {
@@ -225,6 +229,10 @@
     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
     case AddrMode_i12:    return "AddrMode_i12";
     case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
+    case AddrMode_bf:     return "AddrMode_bf";
+    case AddrModeT2_i7s4: return "AddrModeT2_i7s4";
+    case AddrModeT2_i7s2: return "AddrModeT2_i7s2";
+    case AddrModeT2_i7:   return "AddrModeT2_i7";
     }
   }
 
Index: llvm/lib/Target/ARM/ARMInstrFormats.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrFormats.td
+++ llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -109,6 +109,10 @@
 def AddrMode_i12    : AddrMode<16>;
 def AddrMode5FP16   : AddrMode<17>;
 def AddrModeT2_ldrex : AddrMode<18>;
+def AddrMode_bf     : AddrMode<19>;
+def AddrModeT2_i7s4 : AddrMode<20>;
+def AddrModeT2_i7s2 : AddrMode<21>;
+def AddrModeT2_i7   : AddrMode<22>;
 
 // Load / store index mode.
 class IndexMode<bits<2> val> {


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