[PATCH] D60694: [ARM] Introduce separate features for FP registers.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The MVE extension in Arm v8.1-M permits the use of some move, load and
store isntructions which access the FP registers, even if there's no
actual FP support in the processor (in particular, if you have the
integer-only version of MVE).

Therefore, we need separate subtarget features to condition those
instructions on, which are implied by both FP and MVE but are not part
of either.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60694

Files:
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/lib/Target/ARM/ARMPredicates.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/MC/ARM/fullfp16-neg.s
  llvm/test/MC/ARM/mve-fp-registers.s
  llvm/test/MC/ARM/mve-vmov-lane.s
  llvm/test/MC/ARM/single-precision-fp.s
  llvm/test/MC/ARM/vmrs_vmsr.s
  llvm/test/MC/Disassembler/ARM/mve-vmov-lane.txt

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