[PATCH] D60660: [InstCombine] Prune fshl/fshr with masked operands
Shawn Landden via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 15 05:53:59 PDT 2019
shawnl updated this revision to Diff 195146.
shawnl added a comment.
kill newline
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D60660/new/
https://reviews.llvm.org/D60660
Files:
lib/Transforms/InstCombine/InstCombineCalls.cpp
test/Transforms/InstCombine/fsh.ll
Index: test/Transforms/InstCombine/fsh.ll
===================================================================
--- test/Transforms/InstCombine/fsh.ll
+++ test/Transforms/InstCombine/fsh.ll
@@ -560,8 +560,7 @@
}
define i32 @fshl_mask_args_same1(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same1(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -65536
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 16)
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[A:%.*]], 16
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 4294901760 ; 0xffff0000
@@ -570,8 +569,8 @@
}
define i32 @fshl_mask_args_same2(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same2(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65280
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 255
@@ -580,8 +579,7 @@
}
define i32 @fshl_mask_args_same_3(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same_3(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 24)
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[A:%.*]], 24
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 255
@@ -590,9 +588,8 @@
}
define i32 @fshl_mask_args_same5(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same5(
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[A:%.*]], -65536
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], -16777216
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 [[TMP1]], i32 17)
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A:%.*]], 15
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 130560
; CHECK-NEXT: ret i32 [[TMP3]]
;
%tmp2 = and i32 %a, 4294901760 ; 0xfffff00f
@@ -602,8 +599,7 @@
}
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i31> [[A:%.*]], <i31 1000, i31 1000>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[A]], <2 x i31> [[TMP1]], <2 x i31> <i31 10, i31 10>)
+; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
; CHECK-NEXT: ret <2 x i31> [[TMP3]]
;
%tmp1 = and <2 x i31> %a, <i31 1000, i31 1000>
@@ -614,7 +610,7 @@
define <2 x i32> @fshr_mask_args_same_vector2(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: @fshr_mask_args_same_vector2(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1000000, i32 100000>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 29, i32 29>)
+; CHECK-NEXT: [[TMP3:%.*]] = lshr exact <2 x i32> [[TMP1]], <i32 3, i32 3>
; CHECK-NEXT: ret <2 x i32> [[TMP3]]
;
%tmp1 = and <2 x i32> %a, <i32 1000000, i32 100000>
Index: lib/Transforms/InstCombine/InstCombineCalls.cpp
===================================================================
--- lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -2047,8 +2047,13 @@
Type *Ty = II->getType();
unsigned BitWidth = Ty->getScalarSizeInBits();
Constant *ShAmtC;
+
if (match(II->getArgOperand(2), m_Constant(ShAmtC)) &&
!isa<ConstantExpr>(ShAmtC) && !ShAmtC->containsConstantExpression()) {
+ // Left or right might be masked
+ if (SimplifyDemandedInstructionBits(*II))
+ return &CI;
+
// Canonicalize a shift amount constant operand to modulo the bit-width.
Constant *WidthC = ConstantInt::get(Ty, BitWidth);
Constant *ModuloC = ConstantExpr::getURem(ShAmtC, WidthC);
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