[PATCH] D60690: [AArch64] Skip mask checks for masks with an odd number of elements.

Florian Hahn via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 15 05:53:59 PDT 2019


fhahn created this revision.
fhahn added reviewers: t.p.northover, dmgreen, samparker.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

Some checks in isShuffleMaskLegal expect an even number of elements,
e.g. isTRN_v_undef_Mask or isUZP_v_undef_Mask, otherwise they access
invalid elements and crash. This patch adds a check to
isShuffleMaskLegal to ensure there is an even number of elements or
exactly one. The case with one element is relevant for matching some dup
cases. Masks with one element will still cause a crash in isTRN_v_undef_Mask and
isUZP_v_undef_Mask, but I am not sure if that is a realistic scenario. I
can add a separate check or an assertion, if required.

I am not entirely sure if the check is overly restrictive, as I am not
too familiar with the patterns here. We could always push it down to the
problematic functions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60690

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll


Index: llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-unknown-linux -o - | FileCheck %s
+
+define void @test(i32* %p1, i32* %p2) {
+; CHECK-LABEL: test:
+; CHECK-NEXT:    mov w8, #3
+; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    str w8, [x0]
+; CHECK-NEXT:    str w9, [x1]
+; CHECK-NEXT:    ret
+  %tmp = shufflevector <1 x i32> <i32 1>, <1 x i32> undef, <3 x i32> <i32 0, i32 undef, i32 undef>
+  %tmp2 = shufflevector <3 x i32> <i32 2, i32 3, i32 4>, <3 x i32> %tmp, <3 x i32> <i32 0, i32 1, i32 3>
+  %tmp3 = shufflevector <3 x i32> %tmp2, <3 x i32> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef>
+  %tmp4 = shufflevector <6 x i32> undef, <6 x i32> %tmp3, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+  %tmp6 = extractelement <9 x i32> %tmp4, i32 7
+  %tmp8 = extractelement <9 x i32> %tmp4, i32 8
+  store i32 %tmp6, i32* %p1, align 4
+  store i32 %tmp8, i32* %p2, align 4
+  ret void
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7529,7 +7529,8 @@
 }
 
 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
-  if (VT.getVectorNumElements() == 4 &&
+  unsigned NumElts = VT.getVectorNumElements();
+  if (NumElts == 4 &&
       (VT.is128BitVector() || VT.is64BitVector())) {
     unsigned PFIndexes[4];
     for (unsigned i = 0; i != 4; ++i) {
@@ -7549,6 +7550,9 @@
       return true;
   }
 
+  if (NumElts > 1 && NumElts % 2 != 0)
+    return false;
+
   bool DummyBool;
   int DummyInt;
   unsigned DummyUnsigned;


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