[PATCH] D60677: [ARM] Rewrite isLegalT2AddressImmediate

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: efriedma, samparker, olista01.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This does two main things, firstly adding some at least basic addressing modes for i64 types, and secondly treats floats and doubles sensibly when there is no fpu. The floating point change can help codesize in some cases, especially with D60294 <https://reviews.llvm.org/D60294>.

Most backends seems to not consider the exact VT in isLegalAddressingMode, instead switching on type size. That is now what this does when the target does not have an fpu (as the float data will be loaded using LDR's). i64's currently use the address range of an LDRD (even though they may be legalised and loaded with an LDR). This is at least better than marking them all as illegal addressing modes.

The test case has been heavily worked, I'm just showing the differences here for clarity. I have not attempted to do anything with vectors yet. That will need changing once MVE is added.


https://reviews.llvm.org/D60677

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/Analysis/CostModel/ARM/gep.ll
  llvm/test/CodeGen/ARM/large-vector.ll

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