[PATCH] D60559: [TableGen] Include schedule model name in diagnostic.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham updated this revision to Diff 194829.
simon_tatham added a comment.

Adjusted message wording as suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60559/new/

https://reviews.llvm.org/D60559

Files:
  llvm/test/TableGen/SchedModelError.td
  llvm/utils/TableGen/CodeGenSchedule.cpp


Index: llvm/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1935,7 +1935,8 @@
         if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
           PrintError(Inst->TheDef->getLoc(),
                      "No schedule information for instruction '" +
-                         Inst->TheDef->getName() + "'");
+                         Inst->TheDef->getName() + "' in SchedMachineModel '" +
+                     ProcModel.ModelDef->getName() + "'");
           Complete = false;
         }
         continue;
Index: llvm/test/TableGen/SchedModelError.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/SchedModelError.td
@@ -0,0 +1,18 @@
+// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+
+include "llvm/Target/Target.td"
+
+def TestTarget : Target;
+
+// CHECK: [[FILE]]:[[@LINE+1]]:1: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
+def TestInst : Instruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  bits<8> Inst = 0b00101010;
+}
+
+def TestSchedModel : SchedMachineModel {
+  let CompleteModel = 1;
+}
+
+def TestProcessor : ProcessorModel<"testprocessor", TestSchedModel, []>;


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