[llvm] r358223 - [AArch64][GlobalISel] Flesh out vector load/store support for more types.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 11 13:40:01 PDT 2019
Author: aemerson
Date: Thu Apr 11 13:40:01 2019
New Revision: 358223
URL: http://llvm.org/viewvc/llvm-project?rev=358223&view=rev
Log:
[AArch64][GlobalISel] Flesh out vector load/store support for more types.
Some of these were legalizing into smaller vector types unnecessarily,
others were simply not supported yet.
Removed:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=358223&r1=358222&r2=358223&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Apr 11 13:40:01 2019
@@ -224,7 +224,11 @@ AArch64LegalizerInfo::AArch64LegalizerIn
{s32, p0, 32, 8},
{s64, p0, 64, 8},
{p0, p0, 64, 8},
+ {v16s8, p0, 128, 8},
+ {v4s16, p0, 64, 8},
+ {v8s16, p0, 128, 8},
{v2s32, p0, 64, 8},
+ {v4s32, p0, 128, 8},
{v2s64, p0, 128, 8}})
// These extends are also legal
.legalForTypesWithMemDesc({{s32, p0, 8, 8},
@@ -248,7 +252,11 @@ AArch64LegalizerInfo::AArch64LegalizerIn
{s32, p0, 32, 8},
{s64, p0, 64, 8},
{p0, p0, 64, 8},
+ {v16s8, p0, 128, 8},
+ {v4s16, p0, 64, 8},
+ {v8s16, p0, 128, 8},
{v2s32, p0, 64, 8},
+ {v4s32, p0, 128, 8},
{v2s64, p0, 128, 8}})
.clampScalar(0, s8, s64)
.widenScalarToNextPow2(0)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir?rev=358223&r1=358222&r2=358223&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir Thu Apr 11 13:40:01 2019
@@ -12,14 +12,8 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load 8, align 16)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[GEP]](p0) :: (load 8)
- ; CHECK: G_STORE [[LOAD]](<2 x s32>), [[COPY1]](p0) :: (store 8, align 16)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
- ; CHECK: G_STORE [[LOAD1]](<2 x s32>), [[GEP1]](p0) :: (store 8)
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16)
+ ; CHECK: G_STORE [[LOAD]](<4 x s32>), [[COPY1]](p0) :: (store 16)
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir?rev=358223&r1=358222&r2=358223&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir Thu Apr 11 13:40:01 2019
@@ -1,10 +1,58 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64"
+
+ define void @test_load() { ret void }
+ define void @test_store() { ret void }
+
+ define void @store_4xi16(<4 x i16> %v, <4 x i16>* %ptr) {
+ store <4 x i16> %v, <4 x i16>* %ptr
+ ret void
+ }
+
+ define void @store_4xi32(<4 x i32> %v, <4 x i32>* %ptr) {
+ store <4 x i32> %v, <4 x i32>* %ptr
+ ret void
+ }
+
+ define void @store_8xi16(<8 x i16> %v, <8 x i16>* %ptr) {
+ store <8 x i16> %v, <8 x i16>* %ptr
+ ret void
+ }
+
+ define void @store_16xi8(<16 x i8> %v, <16 x i8>* %ptr) {
+ store <16 x i8> %v, <16 x i8>* %ptr
+ ret void
+ }
+
+ define <4 x i16> @load_4xi16(<4 x i16>* %ptr) {
+ %res = load <4 x i16>, <4 x i16>* %ptr
+ ret <4 x i16> %res
+ }
+
+ define <4 x i32> @load_4xi32(<4 x i32>* %ptr) {
+ %res = load <4 x i32>, <4 x i32>* %ptr
+ ret <4 x i32> %res
+ }
+
+ define <8 x i16> @load_8xi16(<8 x i16>* %ptr) {
+ %res = load <8 x i16>, <8 x i16>* %ptr
+ ret <8 x i16> %res
+ }
+
+ define <16 x i8> @load_16xi8(<16 x i8>* %ptr) {
+ %res = load <16 x i8>, <16 x i8>* %ptr
+ ret <16 x i8> %res
+ }
+
+...
---
name: test_load
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_load
@@ -62,7 +110,7 @@ body: |
---
name: test_store
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0, $w1
; CHECK-LABEL: name: test_store
@@ -103,3 +151,171 @@ body: |
%7:_(s128) = G_MERGE_VALUES %6(s64), %6
G_STORE %7(s128), %0(p0) :: (store 16)
...
+---
+name: store_4xi16
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $d0, $x0
+
+ ; CHECK-LABEL: name: store_4xi16
+ ; CHECK: liveins: $d0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p0) :: (store 8 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(p0) = COPY $x0
+ G_STORE %0(<4 x s16>), %1(p0) :: (store 8 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_4xi32
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_4xi32
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[COPY]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(p0) = COPY $x0
+ G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_8xi16
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_8xi16
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[COPY]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(p0) = COPY $x0
+ G_STORE %0(<8 x s16>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_16xi8
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_16xi8
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[COPY]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(p0) = COPY $x0
+ G_STORE %0(<16 x s8>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: load_4xi16
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_4xi16
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
+ ; CHECK: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(p0) = COPY $x0
+ %1:_(<4 x s16>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: load_4xi32
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_4xi32
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LOAD]](<4 x s32>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(p0) = COPY $x0
+ %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: load_8xi16
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_8xi16
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LOAD]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(p0) = COPY $x0
+ %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: load_16xi8
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_16xi8
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LOAD]](<16 x s8>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(p0) = COPY $x0
+ %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<16 x s8>)
+ RET_ReallyLR implicit $q0
+
+...
Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir?rev=358222&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir (removed)
@@ -1,61 +0,0 @@
-# RUN: not llc %s -o - -run-pass=legalizer 2>&1 | FileCheck %s
-
-# Check we don't infinitely loop on (currently) illegal non-extending loads
-# CHECK: LLVM ERROR: unable to legalize instruction
-
---- |
- target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--linux-gnu"
-
- ; Function Attrs: noinline nounwind optnone
- define dso_local float @simulated_vgetq_lane_f16(<8 x half> %vec, i32 %lane) #0 {
- entry:
- %__ret.i = alloca <4 x half>, align 8
- ret float 0.0
- }
-
- attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+crc,+crypto,+fp-armv8,+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
-...
----
-name: simulated_vgetq_lane_f16
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-liveins:
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 16
- adjustsStack: false
- hasCalls: true
- stackProtector: ''
- maxCallFrameSize: 4294967295
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
- - { id: 0, name: __ret.i, type: default, offset: 0, size: 8, alignment: 8,
- stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-constants:
-body: |
- bb.1.entry:
- liveins: $x0
-
- %0:_(p0) = COPY $x0
- %1:_(<4 x s16>) = G_LOAD %0:_(p0) :: (load 8 from %ir.__ret.i)
- $x1 = COPY %1(<4 x s16>)
-
-...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir?rev=358223&r1=358222&r2=358223&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir Thu Apr 11 13:40:01 2019
@@ -33,6 +33,12 @@
define void @load_v2s32(i64 *%addr) { ret void }
define void @load_v2s64(i64 *%addr) { ret void }
+
+ define void @load_4xi16(<4 x i16>* %ptr) { ret void }
+ define void @load_4xi32(<4 x i32>* %ptr) { ret void }
+ define void @load_8xi16(<8 x i16>* %ptr) { ret void }
+ define void @load_16xi8(<16 x i8>* %ptr) { ret void }
+
...
---
@@ -528,3 +534,107 @@ body: |
%1(<2 x s64>) = G_LOAD %0 :: (load 16 from %ir.addr)
$q0 = COPY %1(<2 x s64>)
...
+---
+name: load_4xi16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_4xi16
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.ptr)
+ ; CHECK: $d0 = COPY [[LDRDui]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:gpr(p0) = COPY $x0
+ %1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: load_4xi32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_4xi32
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LDRQui]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:gpr(p0) = COPY $x0
+ %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: load_8xi16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_8xi16
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LDRQui]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:gpr(p0) = COPY $x0
+ %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: load_16xi8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0
+
+ ; CHECK-LABEL: name: load_16xi8
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr)
+ ; CHECK: $q0 = COPY [[LDRQui]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:gpr(p0) = COPY $x0
+ %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+ $q0 = COPY %1(<16 x s8>)
+ RET_ReallyLR implicit $q0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir?rev=358223&r1=358222&r2=358223&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir Thu Apr 11 13:40:01 2019
@@ -30,6 +30,12 @@
define void @store_v2s32(i64 *%addr) { ret void }
define void @store_v2s64(i64 *%addr) { ret void }
+
+ define void @store_4xi16(<4 x i16> %v, <4 x i16>* %ptr) { ret void }
+ define void @store_4xi32(<4 x i32> %v, <4 x i32>* %ptr) { ret void }
+ define void @store_8xi16(<8 x i16> %v, <8 x i16>* %ptr) { ret void }
+ define void @store_16xi8(<16 x i8> %v, <16 x i8>* %ptr) { ret void }
+
...
---
@@ -440,3 +446,107 @@ body: |
G_STORE %1, %0 :: (store 16 into %ir.addr, align 8)
...
+---
+name: store_4xi16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $d0, $x0
+
+ ; CHECK-LABEL: name: store_4xi16
+ ; CHECK: liveins: $d0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: STRDui [[COPY]], [[COPY1]], 0 :: (store 8 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:gpr(p0) = COPY $x0
+ G_STORE %0(<4 x s16>), %1(p0) :: (store 8 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_4xi32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_4xi32
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:gpr(p0) = COPY $x0
+ G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_8xi16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_8xi16
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:fpr(<8 x s16>) = COPY $q0
+ %1:gpr(p0) = COPY $x0
+ G_STORE %0(<8 x s16>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
+---
+name: store_16xi8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+machineFunctionInfo: {}
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $q0, $x0
+
+ ; CHECK-LABEL: name: store_16xi8
+ ; CHECK: liveins: $q0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr)
+ ; CHECK: RET_ReallyLR
+ %0:fpr(<16 x s8>) = COPY $q0
+ %1:gpr(p0) = COPY $x0
+ G_STORE %0(<16 x s8>), %1(p0) :: (store 16 into %ir.ptr)
+ RET_ReallyLR
+
+...
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