[PATCH] D60564: Changes for LLVM PPCISelLowering function combineBVOfConsecutiveLoads

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added inline comments.


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12110
 
-  assert(!(InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
+  assert((InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
          "The loads cannot be both consecutive and reverse consecutive.");
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You put || in the description, but this still says &&. Did you mean ||?


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12111
+  assert((InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
          "The loads cannot be both consecutive and reverse consecutive.");
 
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This text needs to be updated too?



Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60564/new/

https://reviews.llvm.org/D60564