[PATCH] D60562: [X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel.
Herald added a subscriber: arphaman.
Herald added a project: LLVM.

Improves codegen demonstrated by D60512 <https://reviews.llvm.org/D60512> - instructions represented by X86ISD::PERMV/PERMV3 can never memory fold the operand used for their index register.

This patch updates the 'isUseOfShuffle' helper into the more capable 'isFoldableUseOfShuffle' that recognises that the op is used for a X86ISD::PERMV/PERMV3 index mask and can't be folded - allowing us to use broadcast/subvector-broadcast ops to reduce the size of the mask constant pool data.

A further development (also mentioned on D60512 <https://reviews.llvm.org/D60512> ) will be to reduce the size of subvector-broadcast if the upper elements are undef.


Repository:
  rL LLVM

https://reviews.llvm.org/D60562

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512-shuffles/partial_permute.ll
  test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
  test/CodeGen/X86/horizontal-reduce-umax.ll
  test/CodeGen/X86/horizontal-reduce-umin.ll
  test/CodeGen/X86/i64-to-float.ll
  test/CodeGen/X86/masked_compressstore.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/packss.ll
  test/CodeGen/X86/pr30284.ll
  test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
  test/CodeGen/X86/shuffle-strided-with-offset-512.ll
  test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/subvector-broadcast.ll
  test/CodeGen/X86/vector-fshl-256.ll
  test/CodeGen/X86/vector-fshl-512.ll
  test/CodeGen/X86/vector-fshl-rot-256.ll
  test/CodeGen/X86/vector-fshl-rot-512.ll
  test/CodeGen/X86/vector-fshr-256.ll
  test/CodeGen/X86/vector-fshr-512.ll
  test/CodeGen/X86/vector-fshr-rot-256.ll
  test/CodeGen/X86/vector-fshr-rot-512.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-shl-256.ll
  test/CodeGen/X86/vector-shift-shl-512.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll
  test/CodeGen/X86/vector-shuffle-512-v16.ll
  test/CodeGen/X86/vector-shuffle-512-v32.ll
  test/CodeGen/X86/vector-shuffle-512-v8.ll
  test/CodeGen/X86/vector-shuffle-combining-avx.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
  test/CodeGen/X86/vector-shuffle-combining.ll
  test/CodeGen/X86/vector-shuffle-v1.ll

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