[PATCH] D60550: Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake

[Tianle Liu via Phabricator via llvm-commits]

liutianle created this revision.
liutianle added reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang.
Herald added subscribers: llvm-commits, kristina.
Herald added a project: LLVM.

1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS  instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.

VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data. 
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data. 
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision. 
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference


Repository:
  rL LLVM

https://reviews.llvm.org/D60550

Files:
  include/llvm/IR/IntrinsicsX86.td
  lib/Support/Host.cpp
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86IntrinsicsInfo.h
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/avx512bf16-intrinsics.ll
  test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
  test/MC/X86/avx512_bf16-encoding.s
  test/MC/X86/avx512_bf16_vl-encoding.s
  test/MC/X86/intel-syntax-avx512_bf16.s
  test/MC/X86/intel-syntax-avx512_bf16_vl.s
  test/MC/X86/intel-syntax-x86-64-avx512_bf16.s
  test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s
  test/MC/X86/x86-64-avx512_bf16-encoding.s
  test/MC/X86/x86-64-avx512_bf16_vl-encoding.s

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