[llvm] r358144 - [AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 10 16:06:14 PDT 2019
Author: aemerson
Date: Wed Apr 10 16:06:14 2019
New Revision: 358144
URL: http://llvm.org/viewvc/llvm-project?rev=358144&view=rev
Log:
[AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.
The existing isel support already works for p0 once the legalizer accepts it.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=358144&r1=358143&r2=358144&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Wed Apr 10 16:06:14 2019
@@ -486,6 +486,7 @@ AArch64LegalizerInfo::AArch64LegalizerIn
{v8s16, s16},
{v2s32, s32},
{v4s32, s32},
+ {v2p0, p0},
{v2s64, s64}})
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir?rev=358144&r1=358143&r2=358144&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir Wed Apr 10 16:06:14 2019
@@ -39,3 +39,20 @@ body: |
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR
...
+---
+name: legal_v2p0
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ ; CHECK-LABEL: name: legal_v2p0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0)
+ ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>)
+ ; CHECK: RET_ReallyLR
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
+ $q0 = COPY %2(<2 x p0>)
+ RET_ReallyLR
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir?rev=358144&r1=358143&r2=358144&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir Wed Apr 10 16:06:14 2019
@@ -20,6 +20,8 @@
ret <2 x i64> undef
}
+ define void @test_p0(i64 *%a, i64 *%b) { ret void }
+
...
---
name: test_f32
@@ -30,46 +32,6 @@ regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr, preferred-register: '' }
- - { id: 1, class: fpr, preferred-register: '' }
- - { id: 2, class: fpr, preferred-register: '' }
- - { id: 3, class: fpr, preferred-register: '' }
- - { id: 4, class: fpr, preferred-register: '' }
- - { id: 5, class: _, preferred-register: '' }
- - { id: 6, class: _, preferred-register: '' }
- - { id: 7, class: _, preferred-register: '' }
- - { id: 8, class: _, preferred-register: '' }
- - { id: 9, class: _, preferred-register: '' }
- - { id: 10, class: _, preferred-register: '' }
- - { id: 11, class: _, preferred-register: '' }
- - { id: 12, class: _, preferred-register: '' }
- - { id: 13, class: gpr, preferred-register: '' }
- - { id: 14, class: gpr, preferred-register: '' }
- - { id: 15, class: gpr, preferred-register: '' }
- - { id: 16, class: gpr, preferred-register: '' }
-liveins:
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
-constants:
body: |
bb.0 (%ir-block.0):
liveins: $s0, $s1, $s2, $s3
@@ -111,40 +73,6 @@ regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr, preferred-register: '' }
- - { id: 1, class: fpr, preferred-register: '' }
- - { id: 2, class: fpr, preferred-register: '' }
- - { id: 3, class: fpr, preferred-register: '' }
- - { id: 4, class: fpr, preferred-register: '' }
- - { id: 5, class: _, preferred-register: '' }
- - { id: 6, class: _, preferred-register: '' }
- - { id: 7, class: _, preferred-register: '' }
- - { id: 8, class: _, preferred-register: '' }
- - { id: 9, class: gpr, preferred-register: '' }
- - { id: 10, class: gpr, preferred-register: '' }
-liveins:
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
-constants:
body: |
bb.0 (%ir-block.0):
liveins: $d0, $d1, $d2, $d3
@@ -176,42 +104,6 @@ regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
-registers:
- - { id: 0, class: gpr, preferred-register: '' }
- - { id: 1, class: gpr, preferred-register: '' }
- - { id: 2, class: gpr, preferred-register: '' }
- - { id: 3, class: gpr, preferred-register: '' }
- - { id: 4, class: fpr, preferred-register: '' }
- - { id: 5, class: _, preferred-register: '' }
- - { id: 6, class: _, preferred-register: '' }
- - { id: 7, class: _, preferred-register: '' }
- - { id: 8, class: _, preferred-register: '' }
- - { id: 9, class: _, preferred-register: '' }
- - { id: 10, class: _, preferred-register: '' }
- - { id: 11, class: _, preferred-register: '' }
- - { id: 12, class: _, preferred-register: '' }
-liveins:
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
-constants:
body: |
bb.0 (%ir-block.0):
liveins: $w0, $w1, $w2, $w3
@@ -247,44 +139,12 @@ regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
-registers:
- - { id: 0, class: gpr, preferred-register: '' }
- - { id: 1, class: gpr, preferred-register: '' }
- - { id: 2, class: gpr, preferred-register: '' }
- - { id: 3, class: gpr, preferred-register: '' }
- - { id: 4, class: fpr, preferred-register: '' }
- - { id: 5, class: _, preferred-register: '' }
- - { id: 6, class: _, preferred-register: '' }
- - { id: 7, class: _, preferred-register: '' }
- - { id: 8, class: _, preferred-register: '' }
-liveins:
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
-constants:
body: |
bb.0 (%ir-block.0):
- liveins: $x0, $x1, $x2, $x3
+ liveins: $x0, $x1
; CHECK-LABEL: name: test_i64
- ; CHECK: liveins: $x0, $x1, $x2, $x3
+ ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
@@ -299,3 +159,32 @@ body: |
RET_ReallyLR implicit $q0
...
+---
+name: test_p0
+alignment: 2
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $x0, $x1
+
+ ; CHECK-LABEL: name: test_p0
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
+ ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
+ ; CHECK: $q0 = COPY [[INSvi64gpr]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(p0) = COPY $x1
+ %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
+ $q0 = COPY %4(<2 x p0>)
+ RET_ReallyLR implicit $q0
+
+...
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