[PATCH] D60545: [DAGCombiner] narrow shuffle of concatenated vectors

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: dmgreen, sdesmalen, efriedma, RKSimon, craig.topper.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, mcrosier.
Herald added a project: LLVM.

  // shuffle (concat X, undef), (concat Y, undef), Mask -->
  // concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1)

Someone with more ARM NEON experience can confirm, but I think the changes with 'vtrn' are improvements.

The x86 changes look neutral or better. There's one test with an extra instruction, but that could be reversed for a subtarget with the right attributes.

But by default, I think we want to avoid the 256-bit op when possible (in my motivating benchmark, a handful of ymm ops sprinkled into a sequence of xmm ops are triggering frequency throttling on Haswell resulting in signficantly worse perf).


https://reviews.llvm.org/D60545

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/vuzp.ll
  llvm/test/CodeGen/ARM/vzip.ll
  llvm/test/CodeGen/X86/mulvi32.ll
  llvm/test/CodeGen/X86/oddshuffles.ll

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