[PATCH] D60401: [llvm-exegesis] When generating templates with chained instructions, also add templates for helper instructions
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 10 11:28:23 PDT 2019
lebedev.ri added a comment.
To be noted this won't quite help the `-mode=uops`, since there it's the same opcode + randomness:
$ ./bin/llvm-exegesis -mode=uops -opcode-name=CMOV16rr -benchmarks-file=-
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-46b66a.o
---
mode: uops
key:
instructions:
- 'CMOV16rr AX AX R12W i_0x2'
- 'CMOV16rr BP BP DX i_0xe'
- 'CMOV16rr BX BX R10W i_0x3'
- 'CMOV16rr CX CX BX i_0x1'
- 'CMOV16rr DI DI R13W i_0x4'
- 'CMOV16rr DX DX R14W i_0xc'
- 'CMOV16rr SI SI R10W i_0x9'
- 'CMOV16rr R8W R8W SI i_0x2'
- 'CMOV16rr R9W R9W DI i_0x6'
- 'CMOV16rr R10W R10W BP i_0xc'
- 'CMOV16rr R11W R11W BX i_0xd'
- 'CMOV16rr R12W R12W R15W i_0xe'
- 'CMOV16rr R13W R13W DI i_0xc'
- 'CMOV16rr R14W R14W R14W i_0xf'
- 'CMOV16rr R15W R15W R13W i_0x4'
config: ''
register_initial_values:
- 'AX=0x0'
- 'R12W=0x0'
- 'EFLAGS=0x0'
- 'BP=0x0'
- 'DX=0x0'
- 'BX=0x0'
- 'R10W=0x0'
- 'CX=0x0'
- 'DI=0x0'
- 'R13W=0x0'
- 'R14W=0x0'
- 'SI=0x0'
- 'R8W=0x0'
- 'R9W=0x0'
- 'R11W=0x0'
- 'R15W=0x0'
cpu_name: bdver2
llvm_triple: x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
- { key: PdFPU0, value: 0, per_snippet_value: 0 }
- { key: PdFPU1, value: 0, per_snippet_value: 0 }
- { key: PdFPU2, value: 0, per_snippet_value: 0 }
- { key: PdFPU3, value: 0, per_snippet_value: 0 }
- { key: NumMicroOps, value: 1.0135, per_snippet_value: 15.2025 }
error: ''
info: instruction has tied variables, using static renaming.
assembled_snippet: 5541574156415541545366B800006641BC00004883EC08C7042400000000C7442404000000009D66BD000066BA000066BB00006641BA000066B9000066BF00006641BD00006641BE000066BE00006641B800006641B900006641BB00006641BF000066410F42C4660F4EEA66410F43DA660F41CB66410F44FD66410F4CD666410F49F266440F42C666440F46CF66440F4CD566440F4DDB66450F4EE766440F4CEF66450F4FF666450F44FD66410F42C45B415C415D415E415F5DC3
...
Repository:
rL LLVM
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https://reviews.llvm.org/D60401/new/
https://reviews.llvm.org/D60401
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