[PATCH] D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D60441#1461088 <https://reviews.llvm.org/D60441#1461088>, @andreadb wrote:

> I also noticed that this same optimization is done by Fam15h processors (so, it applies to Piledriver). That same paragraph can be found in `AMD Fam15h SOG - Section 5.5 Partial-Register Writes`.
>
> @lebedev.ri can probably verify those numbers for BdVer2.


Sorry, i lost the track here. What's the exact methodology and the test?
Apply this patch and then `$ perf stat ./bin/llvm-exegesis -opcode-name=CVTSI2SSrr_Int -mode=inverse_throughput -num-repetitions=1000000` ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60441/new/

https://reviews.llvm.org/D60441