[PATCH] D60459: SILoadStoreOptimizer pass mischedules s_add,s_addc with interfering s_lshl

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D60459#1460563 <https://reviews.llvm.org/D60459#1460563>, @ronlieb wrote:

> The current problem i am trying to resolve in somewhat analogous to hoisting 1/2 of the 64 bit add instruction pair. Although in this particular situation we are actually sinking 1/2 of the instruction pair into a later position within the same block. And yes, i can see how in the future a new machine instruction pass might choose to hoist one of the instructions into a pred BB. I realize i can write additional code to scan a previous block. However i think its better that passes not hoist part of an instruction pair, especially ones such as these. To that end i would rather see my patch assert so that we are forced to deal with such a situation should it arise.
>  Your example, btw, is a good one for why we should have an IR test for the current problem, rather than an MIR test. An MIR test that runs  just before SILoadStoreOptimizer will not detect the affects of a new pass. Whereas the IR test attached to this patch stands a better chance of detecting the issue.


Why not just bail the optimization if you didn't find a def reasonable close?


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https://reviews.llvm.org/D60459