[PATCH] D60459: SILoadStoreOptimizer pass mischedules s_add,s_addc with interfering s_lshl

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb added a comment.

after looking at the suggestion of using computeRegisterLiveness, I noticed that it does not return the MI where the register in question is most recently defined.
Rather, it informs on liveness within a range. I don’t really see how I would use this method effectively?
The problem I am trying to solve requires identifying a specific instruction that is needed by a subsequent instruction and then adding the identified instruction  to a list constructed by SILoadStoreOptimizer.

Regarding the lit test, i cleaned it up quite a bit and will post a new version shortly. 
I will create a .MIR test from this to specifically test the SILoadStoreOptimizer pass in a direct fashion.
 Any objection to keeping the the .ll test after the MIR test is added?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60459/new/

https://reviews.llvm.org/D60459