[PATCH] D60214: [DAGCombiner] move splat-shuffle after binop with splat constant

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 194344.
spatel added a comment.

Patch updated:

1. Rebase - D60150 <https://reviews.llvm.org/D60150> allowed scalarization of x86 FP ops, so we see that happening in the motivating examples in 'test/CodeGen/X86/scalarize-fp.ll'.
2. Refined the conditions where we can use the existing shuffle mask vs. creating a new splat w/o undef lanes. For example:



  %s = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
  %a = and <2 x i64> %s, <i64 42, i64 42>

To be safe, the new shuffle must actually splat element 1 of the source operand:

  LCPI0_0:
  .quad	42                      ## 0x2a
  .quad	42                      ## 0x2a
  pand	LCPI0_0(%rip), %xmm0
  pshufd	$238, %xmm0, %xmm0      ## xmm0 = xmm0[2,3,2,3]

Rather than:

  pand	LCPI0_0(%rip), %xmm0
  pshufd	$78, %xmm0, %xmm0       ## xmm0 = xmm0[2,3,0,1]


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60214/new/

https://reviews.llvm.org/D60214

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/reg_sequence.ll
  llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
  llvm/test/CodeGen/X86/scalarize-fp.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128-widen.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128-widen.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll

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