[PATCH] D59626: [AMDGPU] Add MachineDCE pass after RenameIndependentSubregs

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

Here is a MIR-reproducer triggering "Multiple connected components in live interval".

For some reason I needed to add "simple-register-coalescing" at the end of the list of passes to run. Otherwise the pass manager decides to discard LIS before dead-mi-elimination.

  # RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,machineverifier,dead-mi-elimination,machineverifier,simple-register-coalescing foo.mir -o /dev/null
  
  ---
  name:            foo
  tracksRegLiveness: true
  body:             |
    bb.0:
      liveins: $sgpr0_sgpr1
  
      %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0
      S_NOP 0, implicit-def %4:sreg_128, implicit %10.sub1:sreg_128
      S_CBRANCH_SCC0 %bb.3, implicit undef $scc
      S_BRANCH %bb.1
  
    bb.1:
      S_CBRANCH_SCC0 %bb.2, implicit undef $scc
      S_BRANCH %bb.3
  
    bb.2:
      %8:sreg_32_xm0 = COPY %4.sub1:sreg_128
      %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
      S_BRANCH %bb.4
  
    bb.3:
      %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0
      %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
      %8:sreg_32_xm0 = COPY %10.sub2:sreg_128
  
    bb.4:
      S_NOP 0, implicit %10
      $sgpr0 = COPY %8:sreg_32_xm0
      $sgpr1 = COPY %7:sreg_32_xm0
      S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1
  ...


Repository:
  rL LLVM

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https://reviews.llvm.org/D59626