[PATCH] D60460: [SelectionDAG] Let computeKnownBits handle OR-like ADDs better

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

This looks ok, but should have more tests.



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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2971-2974
+    KnownBits Known3;
+    Known3 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    KnownZeroHigh = std::min(KnownZeroHigh, Known3.countMinLeadingZeros());
+    KnownZeroLow = std::min(KnownZeroLow, Known3.countMinTrailingZeros());
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When committing, this should/could be a separate change.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2986
 
+    if (Opcode == ISD::ADD && (Known2.Zero | Known3.Zero).isAllOnesValue()) {
+      // This ADD can be treated just like an OR (no common bits set in the
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This **is** correct, what `llvm::haveNoCommonBitsSet()` does.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D60460/new/

https://reviews.llvm.org/D60460