[PATCH] D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, andreadb.
Herald added subscribers: lebedev.ri, gbedwell, hiraditya.
Herald added a reviewer: lebedev.ri.
Herald added a project: LLVM.

Many of our instructions have both a _Int form used by intrinsics and a form
used by other IR constructs. In the EVEX space the _Int versions usually cover
all the capabilities include broadcasting and rounding. While the other version
only covers simple register/register or register/load forms. For this reason
in EVEX, the non intrinsic form is usually marked isCodeGenOnly=1.

In the VEX encoding space we were less consistent, but usually the _Int version
was the isCodeGenOnly version.

This commit makes the VEX instructions match the EVEX instructions. This was
done by manually studying the AsmMatcher table so its possible I missed some
cases, but we should be closer now.

I'm thinking about using the isCodeGenOnly bit to simplify the EVEX2VEX
tablegen code that disambiguates the _Int and non _Int versions. Currently it
checks register class sizes and Record the memory operands come from. I have
some other changes I was looking into for D59266 <https://reviews.llvm.org/D59266> that may break the memory check.

I had to make a few scheduler hacks to keep the _Int versions from being treated
differently than the non _Int version.

I'm not sure to do about the int-to-fpu-forwarding-2.s tests. That seems to be
an issue with the fact that we don't model the tied input on the non _Int
instructions in SSE.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60441

Files:
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrFMA.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-2.s
  llvm/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s

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